VersaLogic VL-586-1, Reference Manual

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External Connections
VL-586-1 Reference Manual Installation – 45
JC – C
OUNTER
/T
IMER
External access to a variety of Counter/Timer signals is available through connector JC.
Table 19: Counter/Timer Connector Pinout
14-Pin Female IDC
JC
Pin
Signal
Name
Function
1 OCTC3
Counter / Timer 3 Out
2 Ground
Ground
3 ICTC4
Counter / Timer 4 In
4 Ground
Ground
5 OCTC4
Counter / Timer 4 Out
6 Ground
Ground
7 ICTC5
Counter / Timer 5 In
8 Ground
Ground
9 OCTC5
Counter / Timer 5 Out
10 Ground
Ground
11 NMI*
STD Bus Non-Maskable Interrupt
12 N/C
13 N/C
Note : The Non-Maskable Interrupt is not available on revision 1 or
revision 2 of the VL-586-1 circuit board.
OCTC3 — Counter / Timer 3 Output. This TTL output signal is the primary output signal
for counter / timer 3.
ICTC4 — Counter / Timer 4 Input. This TTL input signal is used as the primary input
control signal for counter / timer 4.
OCTC4 — Counter / Timer 4 Output.
This TTL output signal is the primary output control
signal for counter / timer 4.
ICTC5 — Counter / Timer 5 Input. This TTL input signal is used as the primary input
control signal for counter / timer 5.
OCTC5 — Counter / Timer 5 Output. This TTL output signal is the primary output control
signal for counter / timer 5.
NMI* — STD Bus Non-Maskable Interrupt. This TTL input signal is used to signal the
CPU of an extremely high priority event, such as imminent loss of power, memory error, or bus
parity error. Interrupts requested through this input cannot be disabled. They are latched by the
CPU, and have the highest priority of all the interrupts. An NMI will abort a DMA transfer if one
is in progress. A low level applied to the NMI* pin cause an INT 02h resulting in a dispatch
through the interrupt vector at 0000:0008h.