VersaLogic VL-586-1, Reference Manual

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Register Summary
VL-586-1 Reference Manual Register Descriptions – 61
I/O
AND
M
EMORY
M
AP
C
ONTROL
R
EGISTER
IOMMAP (WRITE ONLY) 00E2H
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved Reserved Reserved MMAP2 MMAP1 IOMAP2 IOMAP1
Table 40: I/O and Memory Map Register Bit Assignments
Bit Mnemonic Description
D7-D4 — Reserved — These bits have no function. Always read as 0.
D3 MMAP2 Memory Map Select 2 — Selects PC/104 or STD Bus memory access.
MMAP2 = 0 C8000h to CFFFFh = PC/104 Bus
MMAP2 = 1 C8000h to CFFFFh = STD Bus
D2 MMAP1 Memory Map Select 1 — Selects PC/104 or STD Bus memory access.
MMAP1 = 0 D0000h to D7FFFh = PC/104 Bus
MMAP1 = 1 D0000h to D7FFFh = STD Bus
D1 IOMAP2 I/O Map Select 2 — Selects PC/104 or STD Bus I/O access.
IOMAP2 = 0 0100h to 01EFh
0200h to 027Fh
IOMAP2 = 1 0100h to 01EFh
0200h to 027Fh
Note! See I/O map on page 27 for further information.
D0 IOMAP1 I/O Map Select 1 — Selects PC/104 or STD Bus I/O access.
IOMAP1 = 0 02E8h to 02EFh (COM4)
03E8h to 03EFh (COM3)
IOMAP1 = 1 02E8h to 02EFh (COM4)
03E8h to 03EFh (COM3)
Note! See I/O map on page 27 for further information.
}
= STD Bus
}
= PC/104 Bus
}
= PC/104 Bus
}
= STD Bus