VL-1225/6 Analog Input/Output Board
7-11
STD 80 Bus Pinout
COMPONENT SIDE
SOLDER SIDE
Pin
Signal
Flow Description
Pin
Signal
Flow Description
P01
+5VDC
In
Logic Power
P02
+5VDC
In
Logic Power
P03
GND
In
Logic Ground
P04
GND
In
Logic Ground
P05
VBAT
—
Battery Power
P06
DCPDN*
—
DC Power Down
P07
A19/D3
I/O
Address/Data
P08
A23/D7
I/O
Address/Data
P09
A18/D2
I/O
Address/Data
P10
A22/D6
I/O
Address/Data
P11
A17/D1
I/O
Address/Data
P12
A21/D5
I/O
Address/Data
P13
A16/D0
I/O
Address/Data
P14
A20/D4
I/O
Address/Data
P15
A07
In
Address
P16
A15
In
Address
P17
A06
In
Address
P18
A14
In
Address
P19
A05
In
Address
P20
A13
In
Address
P21
A04
In
Address
P22
A12
In
Address
P23
A03
In
Address
P24
A11
In
Address
P25
A02
In
Address
P26
A10
In
Address
P27
A01
In
Address
P28
A09
In
Address
P29
A00
In
Address
P30
A08
In
Address
P31
WR*
In
Write Mem or I/O
P32
RD*
In
Read Mem or I/O
P33
IORQ*
In
I/O Address Select
P34
MEMRQ*
—
Memory Address Select
P35
IOEXP
In
I/O Expansion
P36
BHE* (MEMEX)
In
Byte High Enable (Mem Expan-
sion)
P37
INTRQ1*
Out
Interrupt Request 1
P38
ALE*
—
Address Latch Enable
P39
STATUS1*
—
CPU Status 1
P40
STATUS0*
—
CPU Status 0
P41
BUSAK*
—
Bus Acknowledge
P42
BUSRQ*
—
Bus Request
P43
INTAK*
—
Interrupt Acknowledge
P44
INTRQ*
Out
Interrupt Request
P45
WAITRQ*
—
Wait Request
P46
NMIRQ*
—
Non-maskable Interrupt Request
P47
SYSRESET*
In
System Reset
P48
PBRESET*
—
Push-Button Reset
P49
CLOCK*
—
Clock
P50
CNTRL* (INTRQ2*)
—
Aux Timing
P51
PCO
Out
Priority Chain Out
P52
PCI
In
Priority Chain In
P53
AUX GND
—
AUX Ground
P54
AUX GND
—
AUX Ground
P55
AUX +V
—
AUX Positive (+12VDC)
P56
AUX –V
—
AUX Negative (–12VDC)
* Denotes an active low signal.
— Denotes signal not used on this board.
Figure 7-13. STD 80 Bus Pinout
Reference – STD 80 Bus Pinout
