VL-1225/6 Analog Input/Output Board
4-13
Interrupt Registers
Interrupt Control Register
Interrupt Control Register (ICTRL) — FF08H
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
IE
Figure 4-15. Interrupt Control Register
The Interrupt Control register is a write register used to enable and disable conversion-complete
interrupts.
X
—
Not Used.
These bits have no function in the VL-1225/6. It does not matter what value is written
to them.
IE
—
Interrupt Enable.
Setting this bit to “1” enables interrupts. In this mode an interrupt request is sent
to the CPU when the A/D conversion is complete. Reset this bit to “0” to disable interrupt requests. See
page 5-2 for further information about operating the VL-1225/6 with interrupts. An interrupt software
example is shown on page 6-2.
Interrupt Status Register
Interrupt Status Register (ISTAT) — FF08H
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
IR
Figure 4-16. Interrupt Status Register
The Interrupt Status register is a read register used to determine the current interrupting status of the
VL-1225/6 board.
X
—
Not Used.
These bits have no function in the VL-1225/6. They will always read as “0”.
IR
—
Interrupt Request.
This bit is set to “1” when an interrupt is being requested. It is cleared to “0” when
the CPU acknowledges the interrupt. This bit is always “0” when bit D1 (IE) of ICTRL = 0. In systems
with multiple, non-vectored interrupting devices, this bit can be read to verify that the VL-1225/6 is
responsible for the interrupt.
Registers – Interrupt Registers
