VL-1225/6 Analog Input/Output Board
6-3
0012
read:
0012 C7 06 0002 R 0000
mov
done,0
;Clear done flag
0018 BA 0303
mov
dx,select
;Select channel 0 and Trigger
001B B0 00
mov
al,00h
001D EE
out
dx,al
;Unrelated CPU code can be
;executed here. The VL-1225/6
;requires 40 microseconds to
;complete an A/D conversion.
001E 83 3E 0002 R FF
dcheck:
cmp
done,0ffffh
;Wait here until the ISR executes
0023 75 F9
jnz
dcheck
0025
valid:
;The variable ‘value’ now contains
;valid A/D data.
0025 EB FE
stop:
jmp
stop
;Rest of mainline goes here
0027
init_188:
;VL-188 INTERRUPT INITIALIZATION
0027 BA FF3A
mov
dx,int1
;INT1 CONTROL REGISTER
002A B8 0017
mov
ax,0017h
;D15 0 — = Non Functional Bit
002D EF
out
dx,ax
;D14 0 — = Non Functional Bit
;D13 0 — = Non Functional Bit
;D12 0 — = Non Functional Bit
;D11 0 — = Non Functional Bit
;D10 0 — = Non Functional Bit
;D9 0 — = Non Functional Bit
;D8 0 — = Non Functional Bit
;D7 0 — = Non Functional Bit
;D6 0 SFNM = Normal
;D5 0 C = Non Cascade
;D4 1 LTM = Level Trigger
;D3 0 MSK = Non masked
;D2 1 PR2 = Priority 7
;D1 1 PR1 = Priority 7
;D0 1 PR0 = Priority 7
;Un-mask STD Bus INTRQ* interrupts
;and set to non-cascade mode because
;VL-1225/6 does not provide interrupt
;vector. CPU will internally
;generate type code 13.
002E B8 ---- R
mov
ax,vector
;Install service routine address
0031 8E D8
mov
ds,ax
;into CPU Interrupt Vector Table
assume
ds:vector
0033 C7 06 0034 R 004C R
mov
word ptr vec[0],offset isr
0039 C7 06 0036 R ---- R
mov
word ptr vec[2],seg isr
assume
ds:data
003F B8 ---- R
mov
ax,data
0042 8E D8
mov
ds,ax
0044 C3
ret
0045
init_1225:
;VL-1225/6 INTERRUPT INITIALIZATION
0045 B0 01
mov
al,01h
;CONTROL REGISTER
0047 BA 0300
mov
dx,ictrl
;D7 0 — = Non Functional Bit
004A EE
out
dx,al
;D6 0 — = Non Functional Bit
004B C3
ret
;D5 0 — = Non Functional Bit
;D4 0 — = Non Functional Bit
;D3 0 — = Non Functional Bit
;D2 0 — = Non Functional Bit
;D1 0 — = Non Functional Bit
;D0 1 IE = Interrupt Enable
Software Examples – Interrupt Mode Analog Input
