VeEX VePal TX130M+, User Manual

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Master Sync:
Emulates a SyncE Master clock device out of the Ethernet test port (10/100/1000BaseT or
100/1000BaseX). Uses an internal or external reference clock. The reference clock used on the SyncE link can be
used for Ethernet and PDH testing simultaneously while the clocks are synchronized, the PDH TX port can be used
for BERT testing.
Slave Sync:
Emulates a SyncE Slave clock device from the Ethernet test port (10/100/1000BaseT or
100/1000BaseX). Clock recovered from the SyncE link can be used for Ethernet and PDH testing simultaneously
while the clocks are synchronized. The PDH TX port can be used for BERT testing.
The main application of the Sync mode is to test whether the PDH network and Ethernet network are properly
synchronized.
Clock Input Port (Master Mode Only):
If a non-internal clock source is chosen, the external reference clock is connected
through the Aux Rx port
Clock Source:
Select between an internal or external clock source. Possible external clock sources can be: 2 MHz,
2 Mbps (E1 signal), 10MHz, 25MHz, 125MHz or GPS (1 pps).
Reference Clock Output:
The reference clock used by the SyncE master can be regenerated out of the PDH TX port
(marked Tx on the connector panel) with a different clock format in order to synchronize other network elements.
In Slave mode the Reference Clock Output is the regenerated clock recovered by the SyncE slave.
The clock can be formatted to: 2Mbps (E1 signal), 2.048MHz, 1.544Mbps (T1 signal), 1.544MHz,10MHz, 25MHz, and
125MHz.
Port:
Tx1 - Unbalanced or Tx1 - Balanced
Rate:
Signal rate to transmit to slave clock. Options include: 2 Mbps, 10 MHz, 25 MHz, 125 MHz, or None
Line Code:
HDB3 or AMI
E1 Framing:
Unframed, PCM31, PCM31C, PCM30, or PCM30C
PRBS Pattern
Invert
Press Start to start the connection.
Indicator Symbols - M and SyncE
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