UEi PowerDAQ PDXI-AO Series, User Manual

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Appendix A: Specifications
45
Output High Level 2.0V min @ -4 mA
Output Low Level 0.5V max @ 4 mA
Input Low Voltage 0.0 - 0.8 V
Input High Voltage 2.0 - 5.0 V
Input current 1uA
•
External Event Counter
•
Input Width Measurement
•
Input Period Measurement
•
Event Capture
•
Pulse Width Modulation (PWM)
•
Watchdog Pulse
•
Watchdog Toggle
Note The external clock frequency should be less than the
internal operating frequency divided by 4 (I.e. 16.33/25.00
MHz for 66/100 MHz DSP). The standard PowerDAQ boards
ships with a 66 MHz DSP.
COUNTER/TIMER SPECIFICATIONS:
NoteThe maximum timer frequency is 16.33 MHz for external
clock and 33 MHz for internal clock (66 MHz DSP core). TIO
assumes timer I/O pin, CLKOUT – DSP clock. The minimum
pulse width is 20 ns for an external clock/event.
The following conditions apply:
T
A
= 0
°
C to +100
°
C; C load = 50pF + 2 TTL loads