LISA-C2 series and FW75-C200 - System Integration Manual
UBX-13000620 - R21
Early Production Information
System description
Page 38 of 103
u-blox
Wireless Module
u-blox GPS / GNSS
3.0 V receiver
23
GPIO3
24
GPIO4
1V8
B1
A1
GND
U3
B2
A2
VCCB
VCCA
Unidirectional
Voltage Translator
C
4
C
5
3V0
TxD1
EXTINT0
R1
IN
OUT
GND
GPS LDO
Regulator
SHDN
R2
VMAIN
3V0
U1
21
GPIO2
46
SDA
45
SCL
R4
R5
1V8
SDA_A
SDA_B
GND
U2
SCL_A
SCL_B
VCCA
VCCB
I2C-bus Bidirectional
Voltage Translator
4
V_INT
C1
C2
C3
R3
SDA2
SCL2
VCC
DIR1
DIR2
2
V_BCKP / RSVD
V_BCKP
OE
R7
R6
OE
Figure 20: DDC Application circuit for u-blox GNSS 3.0 V receiver
Reference
Description
Part Number - Manufacturer
R1, R2, R4, R5, R7
4.7 k
Ω
Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
47 k
Ω
Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
R6
200 k
Ω
Resistor 0402 5% 0.1 W
RC0402JR-07200KL - Yageo Phycomp
C2, C3, C4, C5
100 nF Capacitor Ceramic X5R 0402 10% 10V
GRM155R71C104KA01 - Murata
U1, C1
Voltage Regulator for GNSS Receiver and relative
output bypass capacitor
See GNSS Receiver Hardware Integration Manual
U2
I2C-bus Bidirectional Voltage Translator
TCA9406DCUR - Texas Instruments
U3
Generic Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 19: Components for DDC application circuit for u-blox GNSS 3.0 V receiver
Additional considerations
Any external signal connected to the DDC and GPIO interfaces must be tri-stated when the module is in
power-down mode, when the external reset is forced low, and during the module power-on sequence (at
least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If
the external signals connected to the cellular module cannot be tri-stated, insert a multi-channel digital
switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit