Tiger 200T S2505T
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3.4 Advanced Chipset Features
This section describes the settings for the chipset installed on this motherboard.
Please note that the
parameters described in this section are for technically competent users only. Do not change
these values unless you completely understand the consequences of your changes.
SDRAM Cycle Length
Bank 0/1 to
Bank 6/7 DRAM Timing
Settings depend on type of memory installed. These settings are
reserved. [Default settings are
8/10ns
]
Sets the CAS latency timing. [Default setting is
3
]
P2C/C2P Concurrency
System Bios Cacheable
If Enabled, the PCI/AGP Master to CPU cycle can be concurrent
if the Host CPU is performing R/W access to the PCI or slave
devices. [Default is
Enabled
]
Sets ability to cache system BIOS ROM at F0000h-FFFFFh.
[Default is
Disabled
]
Setting is dependent on AGP card. [Default is
Disabled
]
AGP Fast Write
Sets whether you have USB devices. [Default is
Enabled
]
OnChip USB
Enable or disable use of a USB keyboard. [Default is
Disabled
]
USB Keyboard Support
Setting this can compensate for speed differences between the
CPU and PCI bus. [Default is
Enabled
]
CPU to PCI Write Buffer
If Enabled, every write transaction goes to write buffer. Burstable
transactions then burst on the PCI bus, but non-burstable trans-
actions do not. [Default is
Enabled
]
PCI Dynamic Buffering
DRAM Clock
DRAM Clock cycle timing. [Default is
HOST-CLK
]
Memory Hole
Specifies the location of an area or memory that cannot be
addressed on the ISA bus. [Default is
Disabled
]
Bank Interleave
Allows for memory bank interleaving. [Default is
Disabled
]
DRAM Drive Strength
Drive strength, reserved function. [Default setting is
Auto
]
DRAM Drive Value
Drive value, reserved function. [Default setting is
47
]
PCI Delay Transaction
PCI Master 0 WS Write
Sets whether writes to PCI bus are executed with zero wait
states. [Default settings are
Enabled
]
Sets write buffer support in compliance with PCi spec v2.1.
[Default setting is
Enabled
]
Memory Parity / ECC Check
Sets whether the BIOS should enable memory checking auto-
matically when it detects ECC DRAM. [Default is
Disabled
]
PCI#2 Access #1 Retry
Sets whether PCI masters should rotate priority [Default is
Dis-
abled
]
