TE0714 TRM
Revision: v.55
Copyright © 2019 Trenz Electronic GmbH
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http://www.trenz-electronic.de
4.4 Initial Delivery State
Storage device name
Content
Notes
SPI Flash OTP Area
Empty, not
programmed
Except serial number programmed by
flash vendor
SPI Flash Quad Enable bit
Programmed
SPI Flash main array
demo design
eFUSE USER
Not programmed
eFUSE Security
Not programmed
Table 1: Initial delivery state of programmable devices on the module.
4.5 Control Signals
Boot process is controlled by signals on the board to board (B2B) connector.
Signal
Direction
Signal State
Description
BOOTMODE
input
high or open
Master SPI, x4 Mode
low or ground
Slave SelectMAP
PROG_B
input
pulsed low
Clear FPGA configuration (falling edge) and
initiate a new configuration sequenz (next
rising edge).
DONE
output
high
Completion of configuration sequence.
Table 2: Boot signals.
SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are
floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is
not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in
Flash nonvolatile status register.
