Preliminary User's Manual l TQMa65xx UM 0001 l © 2021, TQ-Systems GmbH
Page 16
3.2.2
Memory
3.2.2.1
DDR4 SDRAM
The DDR4 is connected to the AM65xx CPU via a 39-bit wide DDR interface. (32 bits data plus 7 bits ECC.)
The DDR4 SDRAM has a maximum throughput of 1600 MT/s (= 800 MHz DDR4 clock).
A maximum of 4 Gbyte DDR4 SDRAM plus optional ECC can be assembled on the TQMa65xx.
3.2.2.2
eMMC
The AM65XX provides two MMCSD controller. Both MMCSD interfaces are routed to the TQMa65xx connectors.
The eMMC on the TQMa65xx is connected with 8 bit to MMCSD0 and meets eMMC standard v5.1.
Up to 64 Gbyte eMMC can be assembled on the TQMa65xx.
Please note that HS400 is not possible on account of a CPU erratum.
MMCSD1 with 4-bit is intended for the SD card interface.
Devices, which meet SD 4.10 or SDIO 4.0 can be connected on the carrier board, if the eMMC on the TQMa65xx is not assembled.
Figure 3:
Block diagram MMCSD interface
The following eMMC modes are not supported at the AM65xx MMCSD ports:
Table 15:
Unsupported eMMC modes
MMCSD port
MMC
SD card
MMCSD0
−
3.0 V and 1.8 V
−
HS400 DDR: 1.8 V, 2-200 MHz, 8-bit, 400 Mbyte/s
−
UHS II
MMCSD1
−
3.0 V and 1.8 V
−
All 8-bit Modes
−
UHS II
