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6.2.4. Timing of Host Interface (Ultra DMA)
Figure 11 shows the timings of the host interface Ultra DMA word.
*1: In all timing diagrams, the low line indicator is negated and the upper line indicators asserted.
Ultra DMA Mode 2
Timing parameters min (ns) max (ns)
Min time (ns) Max time (ns)
Typical Sustained Average Cycle time
120
Two cycle time (from rising edge to next rising edge of
from falling edge to next falling edge of STROBE)
117
tCYC
Cycle time allowing
55
tDVS
Data valid Setup time
34
tDVH
Data valid Hold time
6
tUI
Unlimited Interlock time
0
tACK
Setup and Hold Time for DMACK-
20
tENV
Envelope time
20
70
tZAD
Minimum Delay time for Driver
0
tZIORDY
Minimum time for DMACK-
20
tFS
First STROBE time
0
170
tRFS
Ready-to-Final STROBE time
50
tRP
Ready-to-Pause time
100
tLI
Limited Interlock time
0
150
tMLI
Interlock with minimum
20
t2CYC
Figure 11 Timings of Host Interface (Ultra DMA Mode 2)
tMLI
tUI
STOP
t2CYC
tFS
tLI
DMACK-
DMARQ
tACK
tCYC
tCYC
t2CYC
tRP
tRFS
tZAD
tZAD
tZIORDY
tZIORDY
tDVS tDVH
tDVS tDVH
tDVS tDVH
tACK
tDVS tDVH
tENV
CRC
DMARDY
STROBE
DD (15:0)
Sender
STROBE
Summary of Contents for R6472 - DVD±RW Drive - IDE
Page 16: ...TS L532A SD R6472 Rev 1 1 10 28 Unit mm Figure 5 1 External Dimensions ...
Page 17: ...TS L532A SD R6472 Rev 1 1 11 28 Unit mm Figure 5 2 External Dimensions ...
Page 19: ...TS L532A SD R6472 Rev 1 1 13 28 Figure 6 Configuration ...
Page 33: ...TS L532A SD R6472 Rev 1 1 27 28 Annex 1 ...
