Toshiba JTMP91C824-S, Manual

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TMP91C824
91C824-93 2008-02-20
3.7.2 Operation of Each Circuit
(1) Prescalers
A 9-bit prescaler generates the input clock to TMRA01.
The
φ
T0 as the input clock to prescaler is a clock divided by 4 which selected using
the prescaler clock selection register SYSCR0<PRCK1:0>.
The prescaler’s operation can be controlled using TA01RUN<TA01PRUN> in the
timer control register. Setting <TA01PRUN> to 1 starts the count; setting
<TA01PRUN> to 0 clears the prescaler to zero and stops operation. Table 3.7.2 shows
the various prescaler output clock resolutions.
Table 3.7.2 Prescaler Output Clock Resolution
at fc
=
33 MHz, fs
=
32.768 kHz
Prescaler Output Clock Resolution
System Clock
Selection
SYSCR1
<SYSCK>
Prescaler Clock
Selection
SYSCR0
<PRCK1:0>
Gear Value
SYSCR1
<GEAR2:0>
φ
T1
φ
T4
φ
T16
φ
T256
1 (fs) XXX 2
3
/fs (244
µ
s) 2
5
/fs (977
µ
s) 2
7
/fs (3.9 ms) 2
11
/fs (62.5 ms)
000 (fc) 2
3
/fc (0.2
µ
s) 2
5
/fc (1.0
µ
s) 2
7
/fc (3.9
µ
s) 2
11
/fc (62.1
µ
s)
001 (fc/2) 2
4
/fc (0.5
µ
s) 2
6
/fc (1.9
µ
s) 2
8
/fc (7.8
µ
s) 2
12
/fc (248.2
µ
s)
010 (fc/4) 2
5
/fc (1.0
µ
s) 2
7
/fc (3.9
µ
s) 2
9
/fc (15.5
µ
s) 2
13
/fc (496.5
µ
s)
011 (fc/8) 2
6
/fc (1.9
µ
s) 2
8
/fc (7.8
µ
s) 2
10
/fc (31.0
µ
s) 2
14
/fc (1024
µ
s)
00
(f
FPH
)
100 (fc/16) 2
7
/fc (3.9
µ
s) 2
9
/fc (15.5
µ
s) 2
11
/fc (62.1
µ
s) 2
15
/fc (993
µ
s)
0 (fc)
10
(fc
/16 clock)
XXX
2
7
/fc (3.9
µ
s) 2
9
/fc (15.5
µ
s) 2
11
/fc (62.1
µ
s) 2
15
/fc (993
µ
s)
xxx: Don’t care
(2) Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks φ T1, φ T4 or φ T16. The clock setting
is specified by the value set in TA01MOD<TA0CLK1:0>.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φ T1, φ T16 or φ T256, or the comparator output (The match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the
up counters and to control their count. A reset clears both up counters, stopping the
timers.