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Toshiba JTMP91C824-S, Manual

The Toshiba JTMP91C824-S user manual is a comprehensive guide designed to assist users in understanding and maximizing the features of this exceptional product. This detailed manual is available for free download from our website, ensuring easy access and convenience for our valued customers.

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TMP91C824 

 91C824-161 

2008-02-20 

 

b. Clock 

synchronization 

In the I

2

C bus mode, in order to wired-AND a bus, a master device which pulls 

down a clock line to low level, in the first place, invalidate a clock pulse of 
another master device which generates a high-level clock pulse. The master 
device with a high-level clock pulse needs to detect the situation and implement 
the following procedure. 

The TMP91C824 has a clock synchronization function for normal data transfer 

even when more than one master exists on the bus. 

The example explains the clock synchronization procedures when two masters 

simultaneously exist on a bus. 

 

 
 
 
 
 
 
 
 
 
 
 

Figure 3.10.8  Clock Synchronization

 

 

As master A pulls down the internal SCL output to the low level at point a, the 

SCL line of the bus becomes the low level. After detecting this situation, master 
B resets a counter of high-level width of an own clock pulse and sets the internal 
SCL output to the low level. 

Master A finishes counting low-level width of an own clock pulse at point b and 

sets the internal SCL output to the high level. Since master B holds the SCL line 
of the bus at the low level, master A wait for counting high-level width of an own 
clock pulse. After master B finishes counting low-level width of an own clock 
pulse at point c and master A detects the SCL line of the bus at the high level, 
and starts counting high level of an own clock pulse. The clock pulse on the bus 
is determined by the master device with the shortest high-level width and the 
master device with the longest low-level width from among those master devices 
connected to the bus. 

(4)

 

Slave address and address recognition mode specification 

When the TMP91C824 is used as a slave device, set the slave address <SA6:0> and 

<ALS> to the I2C0AR. Clear the <ALS> to 0 for the address recognition mode. 

(5)

 

Master/slave selection 

Set the SBI0CR2<MST> to 1 for operating the TMP91C824 as a master device. 

Clear the SBI0CR2<MST> to 0 for operation as a slave device. The <MST> is cleared 
to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost. 

 

Internal SCL output 
(Master A) 

Internal SCL output 
(Master B) 

SCL line 

Reset a counter of 
high-level

 

width of 

a clock

 

pulse 

Wait counting high-level 
width of a clock pulse 

Start counting high-level width of a clock pulse 

a b

c

Summary of Contents for JTMP91C824-S

Page 1: ...TOSHIBA Original CMOS 16 Bit Microcontroller TLCS 900 L1 Series TMP91C824FG Semiconductor Company ...

Page 2: ...T mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode for about 5 clocks of fFPH with IDLE1 or STOP mode IDLE2 is not applicable to this case In this case an interrupt request is kept on hold internally If another interrupt is generated after it has shifted to HALT mode completely halt status can be released without difficultly The priority of this in...

Page 3: ... The TOSHIBA products listed in this document are intended for usage in general electronics applications computer personal equipment office equipment measuring equipment industrial robotics domestic appliances etc These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may ca...

Page 4: ...errupt 12 Chip select wait controller 4 channels 13 Memory management unit Expandable up to 106 Mbytes 4 local areas 8 bank method 14 Interrupts 37 interrupts 9 CPU interrupts Software interrupt instruction and illegal instruction 23 internal interrupts 7 priority levels are selectable 5 external interrupts 7 priority levels are selectable among 4 interrupts are selectable edge mode 15 Input outpu...

Page 5: ...P27 A16 to A23 RD WR HWR PZ2 R W PZ3 BUSRQ P54 BUSAK P55 WAIT P56 CS0 to CS3 P60 to P63 CS2A to E 2 CS P62 P64 to P67 P60 to P67 NMI INT0 to INT3 PB3 to PB6 MLDALM PD7 ALARM MLDALM PD6 10 bit 8 channel AD converter SIO UART IrDA SIO0 8 bit timer TMRA0 SIO UART SIO1 8 bit timer TMRA1 8 bit timer TMRA2 8 bit timer TMRA3 Port 6 Port 8 Port B Port C Port D Serial bus I F SBI H OSC Clock gear Clock dou...

Page 6: ...5 SCOUT PC5 SCLK1 CTS1 PC4 RXD1 PC3 TXD1 PC2 SCLK0 CTS0 PC1 RXD0 PC0 TXD0 EMU1 EMU0 XT2 XT1 RESET AM1 X1 DVSS1 X2 P56 WAIT P65 EA25 CS2C P63 CS3 P62 CS2 CS2A P61 CS1 P60 CS0 P67 CS2E PZ3 R W PZ2 HWR WR RD A0 A1 A2 A3 A5 A6 A7 A8 A9 VREFH A10 VREFL AVSS AVCC P80 AN0 P81 AN1 P82 AN2 P72 SI SCL PB0 TA0IN PB1 TA1OUT PB2 TA3OUT PB3 INT0 PB4 INT1 PB5 INT2 PB6 INT3 P54 BUSRQ P55 BUSAK AM0 DVCC1 P83 AN3 A...

Page 7: ...5 14 P72 2050 118 48 D4 1504 2050 82 A4 918 2045 15 PB0 2050 251 49 D5 1630 2050 83 A3 778 2045 16 PB1 2050 384 50 D6 1757 2050 84 A2 639 2045 17 PB2 2050 517 51 D7 2045 1750 85 A1 499 2045 18 PB3 2050 650 52 P10 2045 1614 86 A0 359 2045 19 PB4 2050 783 53 P11 2045 1478 87 RD 219 2045 20 PB5 2050 916 54 P12 2045 1341 88 WR 80 2045 21 PB6 2050 1049 55 P13 2045 1205 89 PZ2 59 2045 22 P54 2050 1182 5...

Page 8: ... to request bus release P55 BUSAK 1 I O Output Port 55 I O port with pull up resistor Bus acknowledge Signal used to acknowledge bus release P56 WAIT 1 I O Input Port 56 I O port with pull up resistor Wait Pin used to request CPU bus wait 1 N wait states P60 CS0 1 Output Output Port 60 Output port Chip select 0 Outputs 0 when address is within specified address area P61 CS1 1 Output Output Port 61...

Page 9: ...N7 ADTRG 8 Input Input Input Port 80 to 87 port Pin used to input ports Analog input 0 to 7 Pin used to input to AD conveter AD trigger Signal used to request AD start with used to P83 PB0 TA0IN 1 I O Input Port B0 I O port 8 bit timer 0 input Timer 0 input PB1 TA1OUT 1 I O Output Port B1 I O port 8 bit timer 1 output Timer 0 output or timer 1 output PB2 TA3OUT 1 I O Output Port B2 I O port 8 bit ...

Page 10: ...D6 Output port RTC alarm output pin PD7 MLDALM 1 Output Output Port D7 Output port Melody alarm output pin NMI 1 Input Non maskable interrupt request pin Interrupt request pin with programmable falling edge level or with both edge levels programmable AM0 to AM1 2 Input Operation mode Fixed to AM1 0 AM0 1 16 bit external bus or 8 16 bit dynamic sizing Fixed to AM1 0 AM0 0 8 bit external bus fixed E...

Page 11: ...set operation It means that the system clock mode fSYS is set to fc 32 fc 16 1 2 When the reset is accept the CPU Sets as follows the program counter PC in accordance with the reset vector stored at address FFFF00H to FFFF02H PC 0 7 Value at FFFF00H address PC 15 8 Value at FFFF01H address PC 23 16 Value at FFFF02H address Sets the stack pointer XSP to 100H Sets bits IFF2 0 of the status register ...

Page 12: ...MP91C824 Reset Timing Chart Read Write f FPH A23 to A0 Data in D0 to D15 D0 to D15 Sampling After reset released startting 2 waits read cycle Data out Sampling PZ2 input mode RESET RD WR HWR 0FFFF00H Data in Pull up Internal High Z CS2 CS0 CS1 CS3 ...

Page 13: ...Note Address 000FE0H to 00FFFH is assigned for the TOSHIBA reserve area user can t use 16 Mbyte area R R R R R8 16 R d8 16 nnn Internal I O 4 Kbytes Internal RAM 8 Kbytes 64 Kbyte area nn Vector table 256 bytes Internal area 000000H Direct area n 000100H 003000H 010000H External memory FFFF00H FFFFFFH 001000H 000FE0H ...

Page 14: ...DFM 3 standby controller and 4 noise reduction circuit It is used for low power and low noise systems This chapter is organized as follows 3 3 1 Block Diagram of System Clock 3 3 2 SFR 3 3 3 System Clock Controller 3 3 4 Prescaler Clock Controller 3 3 5 Clock Doubler DFM 3 3 6 Noise Reduction Circuits 3 3 7 Standby Controller ...

Page 15: ...clock fSYS is defined as the divided clock of fFPH and one cycle of fSYS is called one state c Triple clock mode trasision Figure Using DMF Instruction Reset fOSCH 32 Release reset Instruction Interrupt STOP mode Stops all circuits NORMAL mode fOSCH gear value 2 IDLE2 mode I O operate IDLE1 mode Operate only oscillator a Single clock mode transition figure b Dual clock mode transition fiigure STOP...

Page 16: ...XTEN RXTEN Warm up timer High low frequency oscillator Lockup timer DFM SYSCR0 WUEF SYSCR2 WUPTM1 0 DFMCR0 ACT1 0 DLUPTM X1 X2 Clock doubler DFM fDFM fOSCH 4 2 16 4 fc 16 fc 8 fc 4 fc 2 fc DFMCR0 ACT1 0 SYSCR1 GEAR2 0 2 4 fc 16 fFPH fSYS 2 fSYS CPU RAM ADC Interrupt controller WDT I O ports Prescaler φT0 SIO0 to SIO1 SBI RTC φT fs φT0 fs φT SYSCR0 XEN RXEN High frequency oscillator 8 Prescaler MLD...

Page 17: ...1 Reserved 7 6 5 4 3 2 1 0 SYSCR1 Bit symbol SYSCK GEAR2 GEAR1 GEAR0 00E1H Read Write R W After reset 0 1 0 0 Function Select system clock 0 fc 1 fs Select gear value of high frequency fc 000 fc 001 fc 2 010 fc 4 011 fc 8 100 fc 16 101 Reserved 110 Reserved 111 Reserved 7 6 5 4 3 2 1 0 SYSCR2 Bit symbol SCOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE 00E2H Read Write R W R W R W R W R W R W R W Aft...

Page 18: ...to 2 5 MHz at 2 0 V 10 write 1BH Figure 3 3 4 SFR for DFM Limitation point on the use of DFM 1 It s prohibited to execute DFM enable disable control in the SLOW mode fs Write to DFMCR0 ACT1 0 10 You should control DFM in the NORMAL mode 2 If you stop DFM operation during using DFM DFMCR0 ACT1 0 10 you shouldn t execute that change the clock fDFM to fOSCH and stop the DFM at the same time Therefore...

Page 19: ...KEY 1st KEY EMCCR1 5AH EMCCR2 A5H in succession write 2nd KEY EMCCR1 A5H EMCCR2 5AH in succession write EMCCR3 Bit symbol ENFROM ENDROM ENPROM FFLAG DFLAG PFLAG 00E6H Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 CS1A write operation flag CS2B 2G write operation flag CS2A write operation flag Function CS1A area detect control 0 Disable 1 Enable CS2B 2G area detect control 0 Disable 1 ...

Page 20: ...example fSYS is set to 1 03 MHz when the 33 MHz oscillator is connected to the X1 and X2 pins 1 Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins or to the XT1 and XT2 pins the warm up timer can be used to change the operation frequency after stable oscillation has been attained The warm up time can be selected using SYSCR2 WUPTM0 1 This warm up timer ca...

Page 21: ...T 2 SYSCR0 Clears and starts warm up timer WUP BIT 2 SYSCR0 JR NZ WUP SET 3 SYSCR1 Changes fSYS from fc to fs RES 7 SYSCR0 Disables high frequency oscillation X Don t care No change Detects stopping of warm up timer fc fs Counts up by fs XEN X1 X2 pins XT1 XT2 pins XTEN Warm up timer End of warm up timer SYSCK System clock fSYS Enables low frequency Clears and starts warm up timer End of warm up t...

Page 22: ...R0 Clears and starts warm up timer WUP BIT 2 SYSCR0 JR NZ WUP RES 3 SYSCR1 Changes fSYS from fs to fc RES 6 SYSCR0 Disables low frequency oscillation X Don t care No change Detects stopping of warm up timer Counts up by fOSCH XEN X1 X2 pins XT1 XT2 pins XTEN Warm up timer End of warm up timer SYSCK System clock fSYS Enables high frequency Clears and starts warm up timer End of warm up timer Chages...

Page 23: ...er value There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing To execute the instruction next to the clock gear switching instruction by the clock gear after changing input the dummy instruction as follows Instruction to execute the write cycle Example SYSCR1 EQU 00E1H LD SYSCR1 XXXX0001B Changes fSYS to fc 4 LD DUM...

Page 24: ...uires time to stabilize This is called the lockup time The following example shows how DFM is used DFMCR0 EQU 00E8H DFMCR1 EQU 00E9H LD DFMCR1 00001011B DFM parameter setting LD DFMCR0 01 0XXXXB Set lockup time to 212 4 MHz Enables DFM operation and starts lockup LUP BIT 5 DFMCR0 JR NZ LUP Detects end of lockup LD DFMCR0 10 0XXXXB Changes fc from 4 MHz to 16 MHz Changes fSYS from 2 MHz to 8 MHz X ...

Page 25: ...LD SYSCR0 11 1 B High frequency oscillator start up warm up start WUP BIT 2 SYSCR0 JR NZ WUP Check for the flag of warm up end LD SYSCR1 0 B Change the system clock fs to fOSCH LD DFMCR0 01 0 B DFM start up lockup start LUP BIT 5 DFMCR0 JR NZ LUP Check for the flag of lockup end LD DFMCR0 10 0 B Change the system clock fOSCH to fDFM OK Low frequency oscillator operation mode fs High frequency osci...

Page 26: ...llator stop LD SYSCR1 1 B Change the system clock fDFM to fs LD DFMCR0 11 B Change the internal clock fc fDFM to fOSCH LD DFMCR0 00 B DFM stop LD SYSCR0 0 B High frequency oscillator stop OK DFM use mode fDFM Set the STOP mode High frequency oscillator operation mode fOSCH DFM stop HALT High frequency oscillator stop LD SYSCR2 01 B Set the STOP mode This command can execute before use of DFM LD DF...

Page 27: ...ontents 5 ROM protection of register contents 1 Reduced drivability for high frequency oscillator Purpose Reduces noise and power for oscillator when a resonator is used Block diagram Setting method The drivability of the oscillator is reduced by writing 0 to EMCCR0 DRVOSCH register By reset DRVOSCH is initialized to 1 and the oscillator starts oscillation by normal drivability when the power supp...

Page 28: ...requency oscillator Purpose Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used Block diagram Setting method The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 EXTIN register X2 pin is always outputted 1 By reset EXTIN is initialized to 0 Note Do not write EMCCR0 EXTIN 1 when using external resonator XT1 p...

Page 29: ...CS B3CS BEXCS MSAR0 MSAR1 MSAR2 MSAR3 MAMR0 MAMR1 MAMR2 MAMR3 2 MMU LOCAL0 1 2 3 3 Clock gear only EMCCR1 EMCCR2 can be written to SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR3 4 DFM DFMCR0 DFMCR1 Operation explanation Execute and release of protection write operation to specified SFR become possible by setting up a double key to EMCCR1 and EMCCR2 register Double key 1st KEY Succession writes in 5AH at EMCCR...

Page 30: ...ee kinds of ROM is fixed as for flash ROM Option program ROM data ROM program ROM are as follows on the logical address memory map 1 Flash ROM Address 400000H to 7FFFFFH 2 Data ROM Address 800000H to BFFFFFH 3 Program ROM Address C00000H to FFFFFFH For these address admission prohibition of detection of write operation sets it up with EMCCR3 ENFROM ENDROM ENPROM And INTP1 interruption occurred wit...

Page 31: ...Seting Operation during IDLE2 Mode Internal I O SFR TMRA01 TA01RUN I2TA01 TMRA23 TA23RUN I2TA23 SIO0 SC0MOD1 I2S0 SIO1 SC1MOD1 I2S1 AD converter ADMOD1 I2AD WDT WDMOD I2WDT SBI SBI0BR0 I2SBI0 b IDLE1 Only the oscillator and the RTC Real time clock and MLD continue to operate c STOP All internal circuits stop operating The operation of each of the different HALT modes is described in Table 3 3 3 Ta...

Page 32: ... the interrupt mask register releasing the the HALT mode is executed In this case interrupt processing and CPU starts executing the instruction next to the HALT instruction but the interrupt request flag is held at 1 Note Usually interrupts can release all halts status However the interrupts NMI INT0 to INT3 INTRTC INTALM0 to INTALM4 which can release the HALT mode may not be able to do so if they...

Page 33: ...HALT mode The priority level Interrupt request level of non maskable interrupts is fixed to 7 the highest priority level There is not this combination type 1 Releasing the HALT mode is executed after passing the warm up time Note When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status hold level H until starting interrupt processing If level L is set be...

Page 34: ...The system clock in the MCU stops The pin status in the IDLE1 mode is depended on setting the register SYSCR2 SELDRV DRVE Table 3 3 6 Table 3 3 7 summarizes the state of these pins in the IDLE mode1 In the halt state the interrupt request is sampled asynchronously with the system clock however clearance of the halt state e g restart of operation is synchronous with it Figure 3 3 7 illustrates the ...

Page 35: ...as been cleared either NORMAL mode or SLOW mode can be selected using the SYSCR0 RSYSCK register Therefore RSYSCK RXEN and RXTEN must be set See the sample warm up times in Table 3 3 5 Figure 3 3 8 illustrates the timing for clearance of the STOP mode halt state by an interrupt Figure 3 3 8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3 3 5 Sample Warm up Times after Clearance ...

Page 36: ...cy after released 9005H HALT NMI 9006H LD XX XX RETI No change Note When different modes are used before and after STOP mode as the above mentioned there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of HALT instruction during 6 states In the system which accepts the interrupts during execution HALT ins...

Page 37: ...L ON ON ON ON ON ON ON ON ON P80 P82 2 P83 2 ADTRG ON ON ON ON P84 P87 2 OFF ON upon port read OFF OFF PB0 TA0IN ON ON OFF ON PB1 PB2 OFF PB3 INT0 ON ON ON ON PB4 INT1 PB5 INT2 PB6 INT3 OFF ON ON OFF ON ON OFF PC0 PC1 RXD0 PC2 SCLK0 CTS0 ON ON OFF ON PC3 PC4 RXD1 PC5 SCLK1 CTS1 ON ON ON ON OFF ON ON PZ2 1 PZ3 1 OFF ON OFF OFF OFF NMI RESET AM0 AM1 ON ON X1 XT1 ON ON ON IDLE1 ON STOP OFF ON The buf...

Page 38: ...P60 0 CS P61 1 CS P62 2 CS A 2 CS P63 3 CS P64 EA24 B 2 CS P65 EA25 C 2 CS P66 D 2 CS P67 E 2 CS ON P70 SCK P71 1 SDA SO OPTTX0 P72 1 SCL ON ON OFF ON PB0 PB1 TA1OUT PB2 TA3OUT ON ON OFF ON PB3 PB6 PC0 TXD0 ON ON OFF ON PC1 PC2 SCLK0 PC3 TXD1 ON ON OFF ON PC4 PC5 SCLK1 OFF PD5 SCOUT PD6 ALARM MLDALM PD7 MLDALM ON PZ2 1 HWR PZ3 1 R W OFF ON ON OFF OFF ON ON X2 IDLE1 ON STOP output H level XT2 ON ON...

Page 39: ... of the CPU interrupt mask register IFF2 0 If the priority level of the interrupt is higher than the value of the interrupt mask register the CPU accepts the interrupt The interrupt mask register IFF2 0 value can be updated using the value of the EI instruction EI num sets IFF2 0 data to num For example specifying EI 3 enables the maskable interrupts which priority level set in the interrupt contr...

Page 40: ...l of accepted interrupt 1 INTNEST INTNEST 1 End PC FFFF00H V Interrupt processing program Count Count 1 Count 0 No Yes Data transfer by micro DMA No Micro DMA processing RETI instruction POP SR POP PC INTNEST INTNEST 1 Clear vector register generating micro DMA transfer and interrupt INTTC0 to INTTC3 Clear interrupt request flag Interrupt vector value V read Interrupt request F F clear Micro DMA s...

Page 41: ...outine RETI restores the contents of program counter PC and status register SR from the stack and decreases the interrupt nesting counter INTNEST by 1 1 Non maskable interrupts cannot be disabled by a user program Maskable interrupts however can be enabled or disabled by a user program A program can set the priority level for each interrupt source A priority level setting of 0 or 7 will disable an...

Page 42: ...FFF3CH 0FH 17 INTALM2 ALM2 64 Hz 0040H FFFF40H 10H 18 INTALM3 ALM3 2 Hz 0044H FFFF44H 11H 19 INTALM4 ALM4 1 Hz 0048H FFFF48H 12H 20 INTTA0 8 bit timer 0 004CH FFFF4CH 13H 21 INTTA1 8 bit timer 1 0050H FFFF50H 14H 22 INTTA2 8 bit timer 2 0054H FFFF54H 15H 23 INTTA3 8 bit timer 3 0058H FFFF58H 16H 24 INTRX0 Serial reception Channel 0 005CH FFFF5CH 17H 25 INTTX0 Serial transmission Channel 0 0060H FF...

Page 43: ...A is disabled and micro DMA processing completes If the decreased result is other than 0 the micro DMA processing completes if it isn t specified the say later burst mode In this case the micro DMA transfer end interrupt INTTC0 to INTTC3 aren t generated If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and t...

Page 44: ...DMA processing can be started by the 24 interrupts shown in the micro DMA start vectors of Table 3 4 1 and by the micro DMA soft start making a total of 25 interrupts Figure 3 4 2 shows the word transfer micro DMA cycle in transfer destination address INC mode except for counter mode the same as for other modes The conditions for this cycle are based on an external 16 bit bus 0 waits transfer sour...

Page 45: ...rred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA If execute soft start during micro DMA transfer by interrupt source micro DMA transfer counter doesn t change Don t use Read modify write instruction to avoid writing to other bits by mistake Symbol Name Address 7 6 5 4 3 2 1 0 DMAR3 DMAR2 DMAR1 DMAR0 R W 0 0 0 0 DMAR DMA request register 89H Prohibit RMW D...

Page 46: ...sfer Transfer source address DEC mode Memory to I O DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn is generated 100 00 Byte transfer 8 states 485 ns 01 Word transfer 12 states 727 ns 10 4 byte transfer Fixed address mode I O to I O DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn is generated 101 00 Counter mode for counting number of times interrupt is generated DMASn DMASn 1 DMACn DMACn 1 If D...

Page 47: ... the same level are generated at the same time the default priority The interrupt with the lowest priority or in other words the interrupt with the lowest vector value is used to determine which interrupt request is accepted first The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channe...

Page 48: ...t controller CPU S Q R V 28H V 2CH V 30H V 34H V 38H V 3CH V 40H V 44H V 48H V 4CH D Q CLR Y1 Y2 Y3 Y4 Y5 Y6 A B C Dn Dn 1 Dn 2 Interrupt request F F Interrupt vector read Micro DMA acknowledge Interrupt request F F Dn 3 A B C interrupt vector read D2 D3 D4 D5 D6 D7 Selector S Q R 0 1 2 3 A B D0 D1 Interrupt vector read Interrupt mask F F Micro DMA request HALT release NMI if INTRQ2 to 0 IFF 2 to ...

Page 49: ...2C IA2M2 IA2M1 IA2M0 R R W R R W INTEALM23 INTALM2 INTALM3 enable 94H 0 0 0 0 0 0 0 0 INTTA1 TMRA1 INTTA0 TMRA0 ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0 R R W R R W INTETA01 INTTA0 INTTA1 enable 95H 0 0 0 0 0 0 0 0 INTTA3 TMRA3 INTTA2 TMRA2 ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0 R R W R R W INTETA23 INTTA2 INTTA3 enable 96H 0 0 0 0 0 0 0 0 INTRTC IRC IRM2 IRM1 IRM0 R R ...

Page 50: ...R W R R W INTETC01 INTTC0 INTTC1 enable 9BH 0 0 0 0 0 0 0 0 INTTC3 INTTC2 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R W R R W INTETC23 INTTC2 NTTC3 enable 9CH 0 0 0 0 0 0 0 0 INTP1 INTP0 IP1C IP1M2 IP1M1 IP1M0 IP0C IP0M2 IP0M1 IP0M0 R R W R R W INTEP01 INTP0 NTP1 enable 9DH 0 0 0 0 0 0 0 0 Interrupt request flag lxxM2 lxxM1 lxxM0 Function Write 0 0 0 Disables interrupt requests 0 0 1...

Page 51: ...R Interrupt clear control 88H Prohibit RMW Interrupt vector 4 Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source When the micro DMA transfer counter value reaches zero the micro DMA transfer end interrupt corres...

Page 52: ...V2 DMA3V1 DMA3V0 R W 0 0 0 0 0 0 DMA3V DMA3 start vector 83H DMA3 start vector 5 Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst Symbol Name Address 7 6 5 4 3 2 1 0 ...

Page 53: ... becomes the Q output If the interrupt input mode is changed from edge mode to level mode the interrupt request flag is cleared automatically INT0 Level Mode If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1 INT0 must then be held at 1 until the interrupt response sequence has been completed If INT0 is set to level mode so as to release a halt state INT0 must ...

Page 54: ...5 P54 1 I O PU Bit BUSRQ P55 1 I O PU Bit BUSAK P56 1 I O PU Bit WAIT Port 6 P60 1 Output Fixed 0 CS P61 1 Output Fixed 1 CS P62 1 Output Fixed 2 CS A 2 CS P63 1 Output Fixed 3 CS P64 1 Output Fixed EA24 B 2 CS P65 1 Output Fixed EA25 C 2 CS P66 1 Output Fixed D 2 CS P67 1 Output Fixed E 2 CS Port 7 P70 P71 P72 1 1 1 I O I O I O PU PU Bit Bit Bit SCK OPTRX0 SO SDA OPTTX0 SI SCL Port 8 P80 to P87 8...

Page 55: ... 0 Port 5 P56 WAIT input with PU 1 0 None None P60 to P64 Output port X 0 0 P60 0 CS output X 1 P61 1 CS output X 1 None 2 CS output X 1 0 P62 A 2 CS output X X 1 P63 3 CS output X 1 None EA24 output X 1 0 P64 B 2 CS output X X 1 EA25 output X 1 0 P65 C 2 CS output X X 1 P66 D 2 CS output X 0 1 Port 6 P67 E 2 CS output X None 0 1 Input port without PU 0 0 0 0 Input port with PU 1 0 0 0 P70 to P72 ...

Page 56: ...ut Note 2 1 1 1 Port C PC5 1 CTS input Note 2 1 0 0 PD5 to PD7 Output port X 0 PD5 SCOUT output X 1 ALARM output 1 1 PD6 MLDALM output 0 1 Port D PD7 MLDALM output X None 1 Input port without PU 0 0 0 Input port with PU 1 0 0 PZ2 to PZ3 Output port X 1 0 PZ2 HWR output X 1 1 Port Z PZ3 W R output X 1 1 None X Don t care Note 1 Port 1 is only use for Port or DATA bus D8 to D15 by setting AM1 and AM...

Page 57: ...ble 3 5 4 shows the pin states after the bus has been released Table 3 5 4 Pin States after bus release The Pin State when the bus is released Pin Name Port Mode Function Mode D0 to D7 Become high impedance High Z D8 to D15 P10 to P17 The state is not changed Do not become to high impedance High Z A0 to A15 First sets all bits to high then sets them to high impedance High Z A16 to 23 P20 to P27 Th...

Page 58: ...r P1CR to 0 and sets port 1 to input mode In addition to functioning as a general purpose I O port port 1 can also function as an address data bus D8 to D15 When AM1 0 and AM0 1 port 10 to 17 always operate data bus function even if it changes P1CR setting Figure 3 5 1 Port 1 Internal data bus Direction control on bit basis P1CR write P10 to P17 D8 to D15 Output buffer Reset P1 read Output latch P...

Page 59: ...6 to A23 Each bit can be set individually for address bus using the function register P2FC Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus Figure 3 5 2 Port 2 Internal data bus Function control on bits basis P2FC write P20 to P27 A16 to A23 Output buffer Reset P2 read Output latch P2 write Port 2 Selector S A B S Internal A16 to A23 ...

Page 60: ... 0 0 0 0 0 0 0 Function 0 Input 1 Output Port 1 I O setting 0 Input 1 Output Port 2 Register 7 6 5 4 3 2 1 0 Bit symbol P27 P26 P25 P24 P23 P22 P21 P20 Read Write R W After reset 1 1 1 1 1 1 1 1 Port 2 Function Register 7 6 5 4 3 2 1 0 Bit symbol P27F P26F P25F P24F P23F P22F P21F P20F Read Write W After reset 1 1 1 1 1 1 1 1 Function 0 Port 1 Address bus A23 to A16 Note Read modify write is prohi...

Page 61: ...unction register P5FC to 0 and sets P54 to P56 to input mode with pull up resistor In addition to functioning as a general purpose I O port port 5 also functions as I O for the CPU s control status signal Figure 3 5 4 Port 5 P55 BUSAK Function control on bit basis S Output latch P55 BUSAK Selector Internal data bus Direction control on bit basis P5CR write P ch Programmable pull up Reset P5FC writ...

Page 62: ...P5 read Internal data bus Direction control on bit basis P5CR write P ch Programmable pull up Reset Internal BUSRQ Function control on bit basis P56 WAIT Internal WAIT S Output latch P5 write P5 read Internal data bus Direction control on bit basis P5CR write Reset Output buffer P ch Programmable pull up ...

Page 63: ... Port 5 Function Register 7 6 5 4 3 2 1 0 Bit symbol P55F P54F Read Write W After reset 0 0 Function 0 Port 1 BUSAK 0 Port 1 BUSRQ Note 1 Read modify write is prohibited for register P5CR P5FC Note 2 When port 5 is used in the input mode P5 register controls the built in pull up resistor Read modify write is prohibited in the input mode or the I O mode Setting the built in pull up resistor may be ...

Page 64: ... connects to CS2 pin but this signal function as P62 after reset Therefore initialized value of output data of P62 is set to 0 If manage chip select by connection many memory to outside after program started must to change port function to chip select function in this program If outputted 1 remain port function program is not run Therefore data setting P6 must to execute after function changing P6...

Page 65: ...0 0 Function Always write 0 0 Port 1 EA25 0 Port 1 EA24 0 Port 1 CS3 0 Port 1 CS2 0 Port 1 CS1 0 Port 1 CS0 Port 6 Function Register 2 7 6 5 4 3 2 1 0 Bit symbol P67F2 P66F2 P65F2 P64F2 P62F2 Read Write W W W W W After reset 0 0 0 0 0 0 0 0 Function 0 P67F 1 CS2E 0 P66F 1 CS2D 0 P65F 1 CS2C 0 P64F 1 CS2B Always write 0 0 P62F 1 CS2A Always write 0 Note Read modify write is prohibited for P6FC and ...

Page 66: ...spective functions Resetting resets the P7FC P7FC2 and P7CR to 0 and sets all bits to input ports 1 Port 70 SCK OPTRX0 Port 70 is a general purpose I O port It is also used as SCK Clock signal for SIO mode and OPTRX0 Receive input for IrDA mode of SIO0 Used as OPTRX0 it is possible to logical invert by P7 P70 0 For port C1 RXD0 or OPTRX0 is used P7FC2 P70F2 Figure 3 5 9 Port 70 Internal data bus S...

Page 67: ...ode of SIO0 Used as OPTTX0 it is possible to logical invert by P7 P71 0 Figure 3 5 10 Port 71 Open drain possible P7ODE ODEP71 SO output Internal data bus Selector A B S P71 SO SDA OPTTX0 P7 read Direction control on bit basis P7CR write Function control on bit basis P7FC write S Output latch P7 write Reset SDA input P ch P7FC2 write C Logical invert TXD0 output Programable pull up Selector A B S ...

Page 68: ... I2C mode for serial bus interface and input for release hard protect Figure 3 5 11 Port 72 Open drain possible P7ODE ODEP72 SCL output Internal data bus Selector A B S Selector A B S P72 SI SCL P7 read Direction control on bit basis P7CR write Function control on bit basis P7FC write S Output latch P7 write Reset SI input SCL input P ch Programable pull up ...

Page 69: ...ter 7 6 5 4 3 2 1 0 Bit symbol P72F P71F P70F Read Write W After reset 0 0 0 Function 0 Port 1 SCL output 0 Port 1 SDA SO output 0 Port 1 SCK output Port 7 Function Register 2 7 6 5 4 3 2 1 0 Bit symbol P71F2 P70F2 Read Write W After reset 0 0 0 Function Always write 0 0 P71F 1 OPTTX0 output SIO0 RXD pin select 0 RXD0 PC1 1 OPTRX0 P70 Port 7 ODE Register 7 6 5 4 3 2 1 0 Bit symbol ODEP72 ODEP71 Re...

Page 70: ... Port 8 Register 7 6 5 4 3 2 1 0 Bit symbol P87 P86 P85 P84 P83 P82 P81 P80 Read Write R After reset Data from external port Note The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1 Figure 3 5 14 Register for Port 8 Internal data bus AD read Conversion result register AD converter Channel selector Port 8 read Port 8 P80 to P87 ...

Page 71: ...interruption is establishes by IIMC register in the interrupt controller Timer output function and external interrupt function can be enabled by writing 1 to the corresponding bits in the port B function register PBFC Resetting resets all bits of the registers PBCR and PBFC to 0 and sets all bits to be input ports 1 PB0 to PB2 Figure 3 5 15 Port B0 to B2 TA0IN PB1 TA1OUT PB2 TA3OUT PB read Timer F...

Page 72: ...nction control on bits basis S Output latch PB write Reset PBFC write INT0 IIMC I0LE I0EDGE Level edge select Rising falling select Selector A B S IIMC I1EDGE I2EDGE I3EDGE Internal data bus PB4 to PB6 INT1 to INT3 PB read Direction control on bits basis PBCR write Function control on bits basis S Output latch PB write Reset PBFC write INT0 to INT3 Selector Rising falling edge detection A B S ...

Page 73: ...Input 1 Output Port B Function Register 7 6 5 4 3 2 1 0 Bit symbol PB6F PB5F PB4F PB3F PB2F PB1F Read Write W After reset 0 0 0 0 0 0 Function 0 Port 1 INT3 0 Port 1 INT2 0 Port 1 INT1 0 Port 1 INT0 0 Port 1 TA3OUT 0 Port 1 TA1OUT Note 1 Read Modify Write is prohibited for the registers PBCR and PBFC Note 2 PB0 TA0IN pin does not have a register changing PORT FUNCTION For example when it is used a...

Page 74: ...g resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports 1 Port C0 C3 TXD0 TXD1 As well as functioning as I O port pins port C0 and C3 can also function as serial channel TXD output pins In case of use TXD0 TXD1 it is possible to logical invert by setting the register PC PC0 3 And port C0 to C3 have a programmable open drain function which can be controlled by the ...

Page 75: ...ins and can also is used as CTS input or SCLK input output for the serial channels In case of use CTS SCLK it is possible to logical invert by setting the register PC PC2 5 Figure 3 5 21 Port C2 and C5 RXD0PC1 RXD1 Selector A B S PC read PC1 RXD0 PC4 RXD1 Ditection control on bit basis PCCR write Reset S Output latch Internal data bus PC write Logical invert Selector A B S Selector A B S PC2 SCLK0...

Page 76: ... Write W W W W After reset 0 0 0 0 Function 0 Port 1 SCLK1 output 0 Port 1 TXD1 0 Port 1 SCLK0 output 0 Port 1 TXD0 Port C ODE Register 7 6 5 4 3 2 1 0 Bit symbol ODEPC3 ODEPC0 Read Write W W After reset 0 0 Function TXD1 0 CMOS 1 Open drain TXD0 0 CMOS 1 Open drain Note 1 Read modify write is prohibited for the registers PCCR PCFC and PCODE Note 2 PC1 RXD0 PC4 RXD1 pins do not have a register cha...

Page 77: ...ting is used the function register PDFC Only PD6 has two output functions which ALARM and MLDALM This selection is used PD PD6 Resetting resets the function register PDFC to 0 and sets all ports to output ports Figure 3 5 23 Port D Figure 3 5 24 Port D Function control on bit basis Output latch PD read Reset PD7 MLDALM MLDALM Output buffer Selector PDFC write PD write S A B Internal data bus Fs cl...

Page 78: ... PD6F PD5F Read Write W After reset 0 0 0 Function 0 Port 1 MLDALM 0 Port 1 ALARM at PD6 1 1 MLDALM at PD6 0 0 Port 1 SCOUT Note Read modify write is prohibited for the registers PDFC Figure 3 5 26 Register for Port D MLDALM Internal data bus Reset S Output latch PD write PD read Function control on bit basis PDFC write S A Y Selector B ALARM PD6 ALARM MLDALM A S Y Selector B PD 0029H PDFC 002AH ...

Page 79: ...unctioning as a general purpose I O port port Z also functions as output for the CPU s control status signal Resetting initializes PZ2 and PZ3 pins to input mode with pull up resistor When the PZ RDE register clearing to 0 outputs the RD strobe used for the peused static RAM of the RD pin even when the internal addressed If the RDE remains 1 the RD strobe signal is output only when the external ad...

Page 80: ...ta bus Direction control on bit basis PZCR write P ch Programmable pull up Reset PZFC write PZ write Output buffer PZ read S B HWR Function conrtol on bit basis S Output latch PZ3 R W Selector Internal data bus Direction control on bit basis PZCR write Reset PZFC write PZ write Output buffer PZ read S A B R W P ch Programmable pull up ...

Page 81: ... 0 Input 1 Output Port Z Function Register 7 6 5 4 3 2 1 0 Bit symbol PZ3F PZ2F Read Write W W After reset 0 0 0 Function Always write 0 0 Port 1 R W 0 Port 1 HWR Note 1 Read modify write is prohibited for registers PZCR and PZFC Note 2 When port Z is used in input mode the PZ register controls the built in pull up resistor Read modify write is prohibited in input mode or I O mode Setting the buil...

Page 82: ... to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3 The chip select wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable disable status the data bus width and the number of waits for each address area The input pin controlling these states is the bus wait request pin WAIT 3 ...

Page 83: ...hip between the start address and the start address register value Memory Start Address Registers for areas CS0 to CS3 7 6 5 4 3 2 1 0 Bit symbol S23 S22 S21 S20 S19 S18 S17 S16 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Determines A23 to A16 of start address Figure 3 6 1 Memory Start Address Register 64 Kbytes Figure 3 6 2 Relationship between Start Address and Start Address Register Val...

Page 84: ... area 7 6 5 4 3 2 1 0 Bit symbol V20 V19 V18 V17 V16 V15 V14 to V9 V8 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Sets size of CS0 area 0 Used for address compare Range of possible settings for CS0 area size 256 bytes to 2 Mbytes Memory Address Mask Register CS1 7 6 5 4 3 2 1 0 Bit symbol V21 V20 V19 V18 V17 V16 V15 to V9 V8 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Sets size of ...

Page 85: ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 F F F F S23 S22 S21 S20 S19 S18 S17 S16 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 7 H Figure 3 6 4 Example Showing How to Set the CS0 Area After a reset MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH B0CS B0E B1CS B1E and B3CS B3E are reset to 0 This disabling the CS0 CS1 and CS3 areas However a...

Page 86: ...y of these addresses may be set as the start address b Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting Hence none of these addresses can be set as the start address Table 3 6 1 Valid Area Sizes for Each CS Area Size Bytes CS Area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M CS0 CS1 CS2 C...

Page 87: ...it 101 3 waits 010 1 N waits 110 4 waits 011 0 waits 111 8 waits Bit symbol B3E B3OM1 B3OM0 B3BUS B3W2 B3W1 B3W0 Read Write W W After reset 0 0 0 0 0 0 0 Functions 0 Disable 1 Enable Chip select output waveform selection 00 For ROM SRAM 01 10 Don t care 11 Data bus width 0 16 bits 1 8 bits Number of waits 000 2 waits 100 Reserved 001 1 wait 101 3 waits 010 1 N waits 110 4 waits 011 0 waits 111 8 w...

Page 88: ...a Bus Width Operand Start Address Memory Data Bus Width CPU Address D15 to D8 D7 to D0 8 bits 2n 0 xxxxx b7 to b0 2n 0 Even number 16 bits 2n 0 xxxxx b7 to b0 8 bits 2n 1 xxxxx b7 to b0 8 bits 2n 1 Odd number 16 bits 2n 1 b7 to b0 xxxxx 2n 0 xxxxx b7 to b0 8 bits 2n 1 xxxxx b15 to b8 2n 0 Even number 16 bits 2n 0 b15 to b8 b7 to b0 2n 1 xxxxx b7 to b0 8 bits 2n 2 xxxxx b15 to b8 2n 1 b7 to b0 xxxx...

Page 89: ...erts a wait of 3 states irrespective of the WAIT pin state 110 4 Inserts a wait of 4 states irrespective of the WAIT pin state 111 8 Inserts a wait of 8 states irrespective of the WAIT pin state A reset sets these bits to 000 2 waits 4 Bus width and wait control for an area other than CS0 to CS3 The chip select wait control register BEXCS controls the bus width and number of waits when memory loca...

Page 90: ...sable status for CS0 to CS3 The CS0 to CS3 pins can also function as pins P60 to P63 To output a chip select signal using one of these pins set the corresponding bit in the port 6 function register P6FC to 1 If a CS0 to CS3 address is specified which is actually an internal I O and RAM area address the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to ...

Page 91: ... A reset clears all bits of the port 6 control register P6CR and the port 6 function register P6FC to 0 and disables output of the CS signal To output the CS signal the appropriate bit must be set to 1 Figure 3 6 7 Example of External Memory Connection RAM and I O use 16 bit bus 74AC08 Not connect Address bus CS 8 bit RAM OE WE TMP91C824 CS Upper byte ROM OE CS Lower byte ROM OE CS 8 bit I O OE WE...

Page 92: ...tion are controlled by 5 byte registers We call control registers SFRs Special function registers Each of the two modules TMRA01 and TMRA23 can be operated independently All modules operate in the same manner hence only the operation of TMRA01 is explained here The contents of this chapter are as follows 3 7 1 Block Diagrams 3 7 2 Operation of Each Circuit 3 7 3 SFRs 3 7 4 Operation in Each Mode 1...

Page 93: ...ator CP0 Match detect Register buffer 0 8 bit timer register TA0REG TA01RUN TA0RDE TA01RUN TA0RUN φT1 φT4 φT16 2 n Overflow TMRA0 interrupt output INTTA0 TA01MOD TA01M1 0 TMRA0 match output TA0TRG Selector φT1 φT16 φT256 Internal bus TA01MOD TA0CLK1 0 TA01MOD TA1CLK1 0 Match detect TMRA1 interrupt output INTTA1 TA01RUN TA1RUN Timer flip flop TA1FF TA1FFCR Timer flip flop output TA1OUT 512 256 128 ...

Page 94: ...A23RUN TA2RDE TA23RUN TA2RUN φT1 φT4 φT16 2 n Overflow TMRA2 interrupt output INTTA2 TA23MOD TA23M1 0 TMRA2 match output TA2TRG Selector φT1 φT16 φT256 Internal bus TA23MOD TA3CLK1 0 Match detect TMRA3 interrup output INTTA3 TA23RUN TA3RUN Timer flip flop TA3FF TA3FFCR Timer flip flop output TA3OUT 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TA23RUN TA23PRUN Internal bus 8 bit up count...

Page 95: ...27 fc 3 9 µs 29 fc 15 5 µs 213 fc 496 5 µs 011 fc 8 26 fc 1 9 µs 28 fc 7 8 µs 210 fc 31 0 µs 214 fc 1024 µs 00 fFPH 100 fc 16 27 fc 3 9 µs 2 9 fc 15 5 µs 2 11 fc 62 1 µs 2 15 fc 993 µs 0 fc 10 fc 16 clock XXX 27 fc 3 9 µs 29 fc 15 5 µs 211 fc 62 1 µs 215 fc 993 µs xxx Don t care 2 Up counters UC0 and UC1 These are 8 bit binary counters which count up the input clock pulses for the clock specified ...

Page 96: ...w occurs in PWM mode or at the start of the PPG cycle in PPG mode Hence the double buffer cannot be used in timer mode A reset initializes TA0RDE to 0 disabling the double buffer To use the double buffer write data to the timer register set TA0RDE to 1 and write the following data to the register buffer Figure 3 7 3 show the configuration of TA0REG Figure 3 7 3 Configuration of TA0REG Note The sam...

Page 97: ...th PB1 When this pin is used as the timer output the timer flip flop should be set beforehand using the port B function register PBCR PBFC Note When the double buffer is enabled for an 8 bit timer in PWM or PPG mode caution is required as explained below If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up counte...

Page 98: ...n Register 7 6 5 4 3 2 1 0 Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN Read Write R W R W After reset 0 0 0 0 0 Function Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 8 bit timer run stop control 0 Stop and clear 1 Run Count up I2TA23 Operation in IDLE2 mode TA23PRUN Run prescaler TA3RUN Run TMRA3 TA2RUN Run TMRA2 Note The values of bits 4 5 6 of TA23RUN are undefined when read Figur...

Page 99: ...ource clock for TMRA0 00 TA0IN pin 01 φT1 10 φT4 11 φT16 00 TA0IN External input 01 φT1 Prescaler 10 φT4 Prescaler 11 φT16 Prescaler TA01MOD TA01M1 0 01 TA01MOD TA01M1 0 01 00 Comparator output from TMRA0 01 φT1 10 φT16 11 φT256 Overflow output from TMRA0 16 bit timer mode 00 Reserved 01 26 source clock 10 27 source clock 11 28 source clock 00 Two 8 bit timers 01 16 bit timer 10 8 bit PPG 11 8 bit...

Page 100: ...T256 TMRA2 clock for TMRA2 00 Reserved 01 φT1 10 φT4 11 φT16 00 Do not set 01 φT1 Prescaler 10 φT4 Prescaler 11 φT16 Prescaler TA23MOD TA23M1 0 01 TA23MOD TA23M1 0 01 00 Comparator output from TMRA2 01 φT1 10 φT16 11 φT256 Overflow output from TMRA2 16 bit timer mode 00 Reserved 01 26 source clock 10 27 source clock 11 28 source clock 00 Two 8 bit timers 01 16 bit timer 10 8 bit PPG 11 8 bit PWM T...

Page 101: ...FF control for inversion 0 Disable 1 Enable TA1FF inversion select 0 TMRA0 1 TMRA1 0 Inversion by TMRA0 1 Inversion by TMRA1 0 Disabled 1 Enabled 00 Inverts the value of TA1FF 01 Sets TA1FF to 1 10 Clears TA1FF to 0 11 Don t care Figure 3 7 7 TMRA Registers TA1FFCR 0105H Control of TA1FF Inverse signal for timer flip flop 1 TA1FF Don t care except in 8 bit timer mode Inversion of TA1FF Read modify...

Page 102: ...FF control for inversion 0 Disable 1 Enable TA3FF inversion select 0 TMRA2 1 TMRA3 0 Inversion by TMRA2 1 Inversion by TMRA3 0 Disabled 1 Enabled 00 Inverts the value of TA3FF 01 Sets TA3FF to 1 10 Clears TA3FF to 0 11 Don t care Figure 3 7 8 TMRA Registers TA3FFCR 010DH Control of TA3FF Inverse signal for timer flip flop 3 TA3FF Don t care except in 8 bit timer mode Inversion of TA3FF Read modify...

Page 103: ...H After reset Undefined bit Symbol Read Write W TA1REG 0103H After reset Undefined bit Symbol Read Write W TA2REG 010AH After reset Undefined bit Symbol Read Write W TA3REG 010BH After reset Undefined Note The above registers are prohibited read modify write instruction Figure 3 7 9 TMRA Registers ...

Page 104: ...RA1 counting Example To generate an INTTA1 interrupt every 10 µseconds at fc 33 MHz set each register as follows Clock state System clock High frequency fc Prescaler clock fFPH MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 1 0 X X Select 8 bit timer mode and select φT1 23 fc s at fc 33 MHz as the input clock TA1REG 0 0 1 0 1 0 0 0 Set TA1REG to 10 µs φT1 23 f...

Page 105: ...lock fFPH 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 Select 8 bit timer mode and select φT1 23 fc s at fc 33 MHz as the input clock TA1REG 0 0 0 0 0 0 1 1 Set the timer register to 1 5 µs φT1 23 fc s 2 3 TA1FFCR X X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detects signal from TMRA1 PBCR X 1 PBFC X 1 X Set PB1 to function as the TA1OUT pin...

Page 106: ...parator Select 8 bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1 Figure 3 7 11 TMRA1 Count up on Signal from TMRA0 TMRA1 up counter when TA1REG 2 TMRA0 up counter when TA0REG 5 1 2 3 4 5 1 1 2 2 3 3 4 5 1 2 1 Comparaot output TMRA0 match TMRA1 match output ...

Page 107: ...f φT16 27 fc s at 33 MHz is used as the input clock for counting set the following value in the registers 0 24 s 27 fc s 62500 F424H e g set TA1REG to F4H and TA0REG to 24H As a result INTTA1 interrupt can be generated every 0 24 s The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG though the up counter UC0 is not be cleared and also INTTA0 is not generate...

Page 108: ...io by TMRA0 The output pulses may be active Low or active High In this mode TMRA1 cannot be used TMRA0 outputs pulses on the TA1OUT pin Figure 3 7 13 8 Bit PPG Output Waveforms t TA0REG and UC0 match Interrupt INTTA0 tH tL TA0REG TA1REG TA1REG and UC0 match Interruput INTTA1 TA1OUT t tL tH When TA1FFC1 0 10 When TA1FFC1 0 01 Example when TA1FFC1 0 01 ...

Page 109: ...Mode If the TA0REG double buffer is enabled in this mode the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0 Use of the double buffer facilitates the handling of low duty waves when duty is varied Figure 3 7 15 Operation of Register Buffer Q3 Shift to register buffer Match with TA0REG and up counter Match with TA1REG TA0REG Value to be compared Register buffer...

Page 110: ...83 53H The duty is to be set to 1 4 t 1 4 20 µs 1 4 5 µs 5 µs 23 fc s 10 Therefore set TA0REG 21 15H 7 6 5 4 3 2 1 0 TA01RUN X X X 0 0 0 Stop TMRA0 and TMRA01 and clear it to 0 TA01MOD 1 0 X X X X 0 1 Set the 8 bit PPG mode and select φT1 as input clock TA0REG 0 0 0 1 0 1 0 1 Write 15H TA1REG 0 1 0 1 0 0 1 1 Write 53H TA1FFCR X X X X 0 1 1 X Set TA1FF enabling both inversion and the double buffer ...

Page 111: ...er UC0 is cleared when 2n counter overflow occurs The following conditions must be satisfied before this PWM mode can be used Value set in TA0REG Value set for 2n counter overflow Value set in TA0REG 0 Figure 3 7 16 8 Bit PWM Waveforms Figure 3 7 17 shows a block diagram representing this mode Figure 3 7 17 Block Diagram of 8 Bit PWM Mode TA1OUT 2n overflow INTTA0 interrupt tPWM PWM cycle TA0REG a...

Page 112: ...s 23 fc s 128 2n Therefore n should be set to 7 Since the low level period is 37 0 µs when φT1 23 fc s set the following value for TA0REG 17 9 µs 23 fc s 74 4AH MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA0 and clear it to 0 TA01MOD 1 1 1 0 0 1 Select 8 bit PWM mode Cycle 27 and select φT1 as the input clock TA0REG 0 1 0 0 1 0 1 0 Write 4AH TA1FFCR X X X X 1 0 1 X Clear TA1FF to 0 enable the ...

Page 113: ...86 µs 7944 µs 993 µs 3972 µs 15888 µs 0 fc 10 fc 16 clock XXX 248 2 µs 993 0 µs 3972 µs 496 5 µs 1986 µs 7944 µs 993 µs 3972 µs 15888 µs XXX Don t care 5 Settings for each mode Table 3 7 4 shows the SFR settings for each mode Table 3 7 4 Timer Mode Setting Registers Register Name TA01MOD TA1FFCR Bit Symbol TA01M1 0 PWM01 00 TA1CLK1 0 TA0CLK1 0 TA1FFIS Function Timer Mode PWM Cycle Upper Timer Inpu...

Page 114: ... FF to CS2 Setup AH 80 FF to CS2 Program ROM Used CS pin CS2 CS2A Maximum memory size 64 Mbytes 64 Mbytes 1 pcs 64 Mbytes 16 Mbytes 4 pcs Used local area BANK number LOCAL3 AH 80 BF 4 Mbytes 16 BANK LOCAL3 AH 80 BF 4 Mbytes 16 BANK Setting CS WAIT Setup AH 80 BF to CS3 Setup AH 80 FF to CS2 Data ROM Used CS pins CS3 EA24 EA25 CS2B CS2C CS2D CS2E Maximum memory size 2 Mbytes COMMON1 14 Mbytes bank ...

Page 115: ...cal area cannot be changed Figure 3 8 1 Logical Address Map 0 1 2 3 4 5 6 7 000000H LOCAL0 COMMON0 LOCAL1 COMMON1 LOCAL3 LOCAL2 COMMON2 Vector area Internal area Overlapped with COMMON area 0 1 2 14 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 Mbyte 100000H 200000H 400000H 1 Mbyte 2 Mbytes 2 Mbytes 2 Mbytes 4 Mbytes 2 Mbytes 2 Mbytes 256 bytes 600000H 800000H C00000H E00000H FFFF00H FFFFFFH CS0 CS0 CS1 CS...

Page 116: ...NK7 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 800000H 1000000H Overlapped with COMMON area BANK8 BANK9 BANK10 BANK11 BANK12 BANK13 BANK14 BANK15 for data ROM 16 Mbytes 6 CS2B CS1 for option program ROM 16 Mbytes CS3 for data RAM 8 Mbytes LOCAL0 LOCAL1 LOCAL2 CS2A for program ROM 16 Mbytes LOCAL3 CS2E CS2C CS2D 000000H 1000000H 000000H 1000000H Internal area BANK0 BANK1 BANK2 BANK3 BANK4 BANK...

Page 117: ...L1EA23 L1EA22 L1EA21 Read Write R W R W After reset 0 0 0 0 Function BANK for LOCAL1 0 Disable 1 Enable Setting BANK number for LOCAL1 001 setting is prohibited because it pretend COMMON 0 area LOCAL2 Register 7 6 5 4 3 2 1 0 Bit symbol L2E L2EA23 L2EA22 L2EA21 Read Write R W R W After reset 0 0 0 0 Function BANK for LOCAL2 0 Disable 1 Enable Setting BANK number for LOCAL2 111 setting is prohibite...

Page 118: ...e of 8 bit bus memory In case of 16 bit bus memory address connection is CPU A1 Memory A0 CPU A2 Memory A1 In case of 8 bit bus memory address connection is CPU A0 Memory A0 CPU A1 Memory A1 Figure 3 8 3 H W Setting Example TMP91C824 FLASH 16 Mbytes 16 bits SRAM 8 Mbytes 8 bits MROM 16 Mbytes 16 bits MROM 64 Mbytes 16 bits Data Address D R WR HWR SRAM CS0 CS1 CS3 EA24 EA25 CS2 Control signals Cont...

Page 119: ... Mbytes LD B1CS 80H Condition 16 bits 2 waits 16 Mbytes Flash ROM CS2 LD MSAR2 C0H Logical address area C00000H to FFFFFFH LD MAMR2 7FH Logical address size 4 Mbytes LD B2CS C3H Condition 16 bits 0 waits 16 Mbytes MROM CS3 LD MSAR3 80H Logical address area 800000H to BFFFFFH LD MAMR3 7FH Logical address size 4 Mbytes LD B3CS 85H Condition 16 bits 3 waits 64 Mbytes MROM CSX LD BEXCS 00H Other 16 bi...

Page 120: ...RG 1400000H Data ROM Start address at BANK5 of LOCAL3 dw 5555H ORG 1800000H Data ROM Start address at BANK6 of LOCAL3 ORG 1C00000H Data ROM Start address at BANK7 of LOCAL3 ORG 2000000H Data ROM Start address at BANK8 of LOCAL3 dw AAAAH ORG 2400000H Data ROM Start address at BANK9 of LOCAL3 ORG 2800000H Data ROM Start address at BANK10 of LOCAL3 ORG 2C00000H Data ROM Start address at BANK11 of LOC...

Page 121: ...3 600000H Physical address of LOCAL2 ORG E00200H LD LOCAL1 84H LOCAL1 BANK4 set 80xxxxH JP 400000H Jump to BANK4 800000H Physical address of LOCAL1 ORG FFFFFFH Program ROM End address at BANK7 COMMON2 of LOCAL2 CS1 ORG 000000H Program ROM Start address at BANK0 of LOCAL1 ORG 200000H Program ROM Start address at BANK1 of LOCAL1 ORG 400000H Program ROM Start address at BANK2 of LOCAL1 ORG 600000H Pr...

Page 122: ...ress conflict with is possible When two kinds or more logical addresses to show common area exist management of BANK is confused We recommend not using The BANK setting BANK address and common address conflict with When it jumps to one memory from other different memory it can set same as the last time setting It needs to write to BANK register of local1 area upper 3 bit address of jumping point A...

Page 123: ...s 0 and 1 can be used independently Both channels operate in the same fashion except for the following points hence only the operation of channel 0 is explained below Table 3 9 1 Differences between Channels 0 to 1 Channel 0 Channel 1 Pin Name TXD0 PC0 RXD0 PC1 CTS0 SCLK0 PC2 TXD1 PC3 RXD1 PC4 CTS1 SCLK1 PC5 IrDA Mode Yes No This chapter contains the following sections 3 9 1 Block Diagrams 3 9 2 O...

Page 124: ... Start Stop Start Stop Parity 7 7 7 Bit0 1 2 3 4 5 6 Start 8 7 Stop Bit0 1 2 3 4 5 6 Start Stop Bit8 7 When Bit8 1 address Select code is denoted When Bit8 0 data is denoted Mode 0 I O interface mode Transfer direction Mode 1 7 bit UART mode Mode 2 8 bit UART mode Mode 3 9 bit UART mode No parity Parity No parity Parity 7 Bit0 1 2 3 4 5 6 Wakeup function ...

Page 125: ...OC SC0MOD0 WU Receive counter UART only 16 Serial channel interrupt control Transmision counter UART only 16 Transmission control Receive control Receive buffer 1 Shift register RB8 Receive buffer 2 SC0BUF Error flag SIOCLK UART mode SC0MOD0 SC1 0 SC0MOD0 SM1 0 TB8 Transmission buffer SC0BUF INT request INTRX0 INTTX0 SC0CR OERR PERR FERR CTS0 Concurrent with PC2 SC0MOD0 CTSE RXD0 Concurrent with P...

Page 126: ...6 Serial channel interrupt control Transmision counter UART only 16 Transmission control Receive control Receive buffer 1 Shift register RB8 Receive buffer 2 SC1BUF Error flag SIOCLK UART mode SC1MOD0 SC1 0 SC1MOD0 SM1 0 TB8 Transmission buffer SC1BUF INT request INTRX1 INTTX1 SC1CR OERR PERR FERR CTS1 Concurrent with PC5 SC1MOD0 CTSE RXD1 Concurrent with PC4 PE SC1CR EVEN TXDCLK SC1MOD0 RXE Parit...

Page 127: ...e 3 9 2 Prescaler Clock Resolution to Baud Rate Generator Prescaler Output Clock Resolution Select System Clock SYSCR1 SYSCK Select Prescaler Clock SYSCR0 PRCK1 0 Gear Value SYSCR1 GEAR2 0 φT0 φT2 φT8 φT32 1 fs XXX 22 fs 24 fs 26 fs 28 fs 000 fc 22 fc 24 fc 26 fc 28 fc 001 fc 2 23 fc 25 fc 27 fc 29 fc 010 fc 4 24 fc 26 fc 28 fc 210 fc 011 fc 8 25 fc 27 fc 29 fc 211 fc 00 fFPH 100 fc 16 26 fc 28 fc...

Page 128: ...tings BR0ADD BR0K3 0 are ignored The baud rate generator divides the selected prescaler clock by N which is set in BR0CK BR0S3 0 N 1 2 3 16 2 When BR0CR BR0ADDE 1 The N 16 K 16 division function is enabled The baud rate generator divides the selected prescaler clock by N 16 K 16 using the value of N set in BR0CR BR0S3 0 N 2 3 15 and the value of K set in BR0ADD BR0K3 0 K 1 2 3 15 Note If N 1 or N ...

Page 129: ...8 MHz the input clock frequency φT0 the frequency divider N BR0CR BR0S3 0 7 K BR0ADD BR0K3 0 3 and BR0CR BR0ADDE 1 the baud rate in UART mode is as follows Clock state System clock High frequency fc Clock gear 1 fc Prescaler clock System clock Baud rate 16 4 8 106 4 7 13 16 16 9600 bps Table 3 9 3 show examples of UART mode transfer rates Additionally the external clock input is available in the s...

Page 130: ...00 4 96 000 24 000 6 000 1 500 5 76 800 19 200 4 800 1 200 8 48 000 12 000 3 000 0 750 A 38 400 9 600 2 400 0 600 10 24 000 6 000 1 500 0 375 27 0336 B 38 400 9 600 2 400 0 600 29 4912 1 460 800 115 200 28 800 7 200 3 153 600 38 400 9 600 2 400 4 115 200 28 800 7 200 1 800 6 76 800 19 200 4 800 1 200 9 51 200 12 800 3 200 0 800 C 38 400 9 600 2 400 0 600 F 30 720 7 680 1 920 0 480 10 28 800 7 200 ...

Page 131: ...f data each data bit is sampled three times on the 7th 8th and 9th clock cycles The value of the data bit is determined from these three samples using the majority rule For example if the data bit is sampled respectively as 1 0 and 1 on 7th 8th and 9th clock cycles the received data bit is taken to be 1 A data bit sampled as 0 0 and 1 is taken to be 0 5 Receiving control In I O interface mode In S...

Page 132: ... 9 bit UART mode the wakeup function for the slave controller is enabled by setting SC0MOD0 WU to 1 in this mode INTRX0 interrupts occur only when the value of SC0CR RB8 is 1 7 Transmission counter The transmission counter is a 4 bit binary counter which is used in UART mode and which like the receiving counter counts the SIOCLK clock pulses a TXDCLK pulse is generated every 16 SIOCLK clock pulses...

Page 133: ...a handshake function can be easily configured by setting any port assigned to be the RTS function The RTS should be output high to request send data halt after data receive is completed by software in the RXD interrupt routine Figure 3 9 5 Handshake Function Note 1 If the CTS signal goes high during transmission no more data will be sent after completion of the current transmission Note 2 Transmis...

Page 134: ...is added after the data has been transferred to receiving buffer 2 SC0BUF and then compared with SC0BUF RB7 in 7 bit UART mode or with SC0CR RB8 in 8 bit UART mode If they are not equal a parity error is generated and the SC0CR PERR flag is set 11 Error flags Three error flags are provided to increase the reliability of data reception 1 Overrun error OERR If all the bits of the next data item have...

Page 135: ...a 1 bit period to allow the stop bit to be transferred to allow checking for a framing error Transmitting Mode 9 Bits 8 Bits Parity 8 Bits 7 Bits Parity 7 Bits Interrupt timing Just before stop bit is transmitted Just before stop bit is transmitted Just before stop bit is transmitted b I O interface SCLK output mode Immediately after the last bit See Figure 3 9 19 Transmission interrupt timing SCL...

Page 136: ...k SCLK0 input Figure 3 9 7 Serial Mode Control Register SIO0 SC0MOD0 SC0MOD0 0202H Serial transmission clock source UART 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock SCLK0 input Note The clock selection for the I O interface mode is controlled by the serial control register SC0CR Serial transmission mode 00 I O Interface mode 01 7 bit mode 10 8...

Page 137: ... input Figure 3 9 8 Serial Mode Control Register SIO1 SC1MOD0 SC1MOD0 020AH Serial transmission clock source for UART 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock SCLK1 input Serial transmission mode 00 I O Interface mode 01 7 bit mode 10 8 bit mode 11 UART mode 9 bit mode Wakeup function 0 Receive disabled 1 Receive enabled Receiving function ...

Page 138: ... flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 9 9 Serial Control Register SIO0 SC0CR SC0CR 0201H I O interface input clock selection Framing error flag Parity error flag Overrun error flag 0 Transmits and receivers data on rising edge of SCLK0 1 Transmits and receivers data on falling edge SCLK0 Edge selection for SCLK pin I O mode 0 Disable...

Page 139: ...gs are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 9 10 Serial Control Register SIO1 SC1CR SC1CR 0209H I O interface input clock select Framing error flag Parity error flag Overrun error flag 0 Transmits and receives data on rising edge of SCLK1 1 Transmits and receives data on falling edge of SCLK1 Edge selection for SCKL pin I O mode 0 Disabled 1 E...

Page 140: ... N 15 0000 N 16 0000 Disable Disable 0001 K 1 to 1111 K 15 Disable Divided by N 16 K 16 Divided by N Note1 Availability of 16 K 16 division function N UART Mode I O Mode 2 to 15 1 16 The baud rate generator can be set 1 in UART mode and disable 16 K 16 division function Don t use in I O interface mode Note2 Set BR0CR BR0ADDE to 1 after setting K K 1 to 15 to BR0ADD BR0K3 0 when 16 K 16 division fu...

Page 141: ... N 15 0000 N 16 0000 Disable Disable 0001 K 1 to 1111 K 15 Disable Disabled by N 16 K 16 Divided by N Note1 Availability of 16 K 16 division function N UART Mode I O Mode 2 to 15 1 16 The baud rate generator can be set 1 in UART mode and disable 16 K 16 division function Don t use in I O interface mode Note2 Set BR1CR BR1ADDE to 1 after setting K K 1 to 15 to BR1ADD BR1K3 0 when 16 K 16 division f...

Page 142: ...SIO0 SC0BUF 7 6 5 4 3 2 1 0 Bit symbol I2S0 FDPX0 Read Write R W R W After reset 0 0 Function IDLE2 0 Stop 1 Run Duplex 0 Half 1 Full Figure 3 9 14 Serial Mode Control Register 1 SIO0 SC0MOD1 SC0MOD1 0205H RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 TB7 TB6 TB2 TB1 TB0 TB3 TB4 TB5 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 SC0BUF 0200H Transmission Receiving ...

Page 143: ...SIO1 SC1BUF 7 6 5 4 3 2 1 0 Bit symbol I2S1 FDPX1 Read Write R W R W After reset 0 0 Function IDLE2 0 Stop 1 Run Duplex 0 Half 1 Full Figure 3 9 16 Serial Mode Control Register 1 SIO1 SC1MOD1 SC1MOD1 020DH RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 SC1BUF 0208H Transmission Receiving ...

Page 144: ...LK Figure 3 9 17 SCLK Output Mode Connection Example Figure 3 9 18 SCLK Input Mode Connection Example Output extension TMP91C824 TXD SCLK Port Input extension TC74HC595 or equivalent TC74HC165 or equivalent TMP91C824 A B C D E F G H RXD SCLK Port Shift register A B C D E F G H SI SCK RCK QH CLOCK L S Shift register TMP91C824 TXD SCLK Port TMP91C824 A B C D E F G H RXD SCLK Port Shift register A B ...

Page 145: ... output on the TXD0 pin when the SCLK0 input becomes active after the data has been written to the transmission buffer by the CPU When all data is output INTES0 ITX0C will be set to generate INTTX0 interrupt Figure 3 9 20 Transmitting Operation in I O Interface Mode SCLK0 input mode SCLK0input SCLKS 0 Rising edge mode SCLK0 input SCLKS 1 Falling edge mode Bit0 Bit1 TXD0 ITX0C INTTX0 Interrupt requ...

Page 146: ... SCLK input mode the data is shifted to receiving buffer 1 when the SCLK input becomes active after the receive interrupt flag INTES0 IRX0C is cleared by reading the received data When 8 bit data is received the data will be shifted to receiving buffer 2 SC0BUF according to the timing shown below and INTES0 IRX0C will be set again to be generate INTRX0 interrupt Figure 3 9 22 Receiving Operation i...

Page 147: ... High frequency fc Clock gear 1 fc Prescaler clock fFPH Main routine 7 6 5 4 3 2 1 0 Set the INTTX0 level to 1 INTES0 0 0 1 0 0 0 Set the INTRX0 level to 0 PCCR 1 0 1 Set PC0 PC1 and PC2 to function as the TXD0 RXD0 and SCLK0 pins respectively PCFC X X X 1 X 1 SC0MOD0 0 0 Select I O interface mode SC0MOD1 1 1 X X X X X X Select full duplex mode SC0CR 0 SCLK output transmit on negative edge receive...

Page 148: ...nction as the TXD0 pin SC0MOD0 0 1 0 1 Select 7 bit UART mode SC0CR 1 1 Add even parity BR0CR 0 0 1 0 0 1 0 1 Set the transfer rate to 2400 bps INTES0 1 0 0 Enable the INTTX0 interrupt and set it to interrupt level 4 SC0BUF Set data for transmission X Don t care No change 3 Mode 2 8 bit UART mode 8 bit UART mode is selected by setting SC0MOD0 SM1 0 to 10 In this mode a parity bit can be added use ...

Page 149: ...ta X Don t care No change 4 Mode 3 9 bit UART mode 9 bit UART mode is selected by setting SC0MOD0 SM1 0 to 11 In this mode parity bit cannot be added In the case of transmission the MSB 9th bit is written to SC0MOD0 TB8 In the case of receiving it is stored in SC0CR RB8 When the buffer is written and read the MSB is read or written first before the rest of the SC0BUF data Wakeup function In 9 bit ...

Page 150: ...de The controller whose code matches clears its WU bit to 0 5 The master controller transmits data to the specified slave controller whose SC0MOD WU bit is cleared to 0 The MSB Bit8 TB8 is cleared to 0 6 The other slave controllers whose WU bits remain at 1 ignore the received data because their MSBs Bit8 or RB8 are set to 0 disabling INTRX0 interrupts The slave controller WU bit 0 can transmit da...

Page 151: ... INTRX0 interrupt and set it to interrupt level 5 SC0MOD0 1 1 1 1 1 0 Set fSYS as the transmission clock for 9 bit UART mode SC0BUF 0 0 0 0 0 0 0 1 Set the select code for slave controller 1 INTTX0 interrupt SC0MOD0 0 Set TB8 to 0 SC0BUF Set data for transmission Setting the slave controller Main PCCR X X 0 1 PCFC X X X X 1 PCODE X X X X X X 1 Set PC1 to RXD0 and PC0 to TXD0 Open drain output INTE...

Page 152: ...m outputs 0 Figure 3 9 25 Modulation Example of Transfer Data 2 Modulation of the receive data When the receive data has the effective high level pulse width Software selectable the modem outputs 0 to SIO0 Otherwise the modem outputs 1 to SIO0 The receive pulse logic is also selectable by SIRCR RXSEL Figure 3 9 26 Demodulation Example of Receive Data Receive data Transmisison data IR demodulator I...

Page 153: ...DA use baud rate generator in SIO0 by setting 01 to SC0MOD0 SC1 0 To use another source TA0TRG fSYS and SCLK0 input are not allowed 2 As the IrDA 1 0 physical layer specification the data transfer speed and infra red pulse width is specified Table 3 9 4 Baud Rate and Pulse Width Specifications Baud Rate Modulation Rate Tolerance of rate Pulse Width Minimum Pulse Width Typical Pulse Width Maximum 2...

Page 154: ...e width 16 k 16 division function can not be used Table 3 9 5 shows Baud rate and pulse width for 16 k 16 division function Table 3 9 5 Baud Rate and Pulse Width for 16 k 16 Division Function Baud Rate Pulse Width 115 2 kbps 57 6 kbps 38 4 kbps 19 2 kbps 9 6 kbps 2 4 kbps T 3 16 T 1 16 Can be used 16 k 16 division function Can not be used 16 k 16 division function Can not be set to 1 16 pulse widt...

Page 155: ...Select receive pulse width Set effective pulse width for equal or more than 2x value 1 100ns Can be set 1 to 4 Can not be set 0 15 Select receive pulse width Formula Effective pulse width 2x Value 1 100ns x 1 fFPH 0000 Cannot be set 0001 Equal or more than 4x 100 ns to 1110 Equal or more than 30x 100 ns 1111 Can not be set Receive operation 0 Disabled 1 Enabled Transmit operation 0 Disabled 1 Enab...

Page 156: ...R P72C 70C P7FC P72F 70F I 2 C bus mode 11 11X 11X Clocked synchronous 8 bit SIO mode XX 011 010 111 X Don t care 3 10 1 Configuration Figure 3 10 1 Serial Bus Interface SBI I2 C bus clock sync control Noise canceller Shift register SBI0CR2 SBI0SR SBI0DBR INTSBI interrupt request φT SBI control register 2 SBI status register I2 C bus address register SBI data buffer register SBI control register 1...

Page 157: ... section 3 10 4 I2C Bus Mode Control and 3 10 7 Clocked Synchronous 8 Bit SIO Mode Control 3 10 3 The Data Formats in the I2 C Bus Mode The data formats in the I2C bus mode is shown below a Addressing format b Addressing format with restart c Free data format Data transferred from master device to slave device S Start condition R W Direction bit ACK Acknowledge bit P Stop condition Figure 3 10 2 D...

Page 158: ...put fscl Hz Software reset state monitor SWRMON at read 0 During software reset 1 Initial data Acknowledge mode specification 0 Not generate clock pulse for acknowledge signal 1 Generate clock pulse for acknowledge signal Number of bits transferred ACK 0 ACK 1 BC2 0 Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7...

Page 159: ...g mode selection Note 2 00 Port mode Serial bus interface output disabled 01 Clocked synchronous 8 bit SIO mode 10 I2 C bus mode 11 Reserved INTSBI interrupt request 0 Don t care 1 Cancel interrupt request Start stop condition generation 0 Generates the stop condition 1 Generates the start condition Transmitter receiver selection 0 Receiver 1 Transmitter Master slave selection 0 Slave 1 Master Not...

Page 160: ... bit monitor 0 0 1 1 Last received bit monitor 0 Last received bit was 0 1 Last received bit was 1 GENERAL CALL detection monitor 0 Undetected 1 GENERAL CALL detected Slave address match detection monitor 0 Undetected 1 Slave address match or GENERAL CALL detected Arbitration lost detection monitor 0 1 Arbitration lost INTSBI interrupt request monitor 0 Interrupt requested 1 Interrupt canceled I2 ...

Page 161: ... transmitted data start from the MSB Bit7 Receiving data is placed from LSB Bit0 Note 2 SBIDBR can t be read the written data Therefore read modify write instruction e g BIT instruction is prohibitted Note 3 Written data in SBI0DBR is cleared by INTSBI signal I2 C Bus Address Register 7 6 5 4 3 2 1 0 Bit symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read Write W After reset 0 0 0 0 0 0 0 0 Function Slave...

Page 162: ... mode 2 Number of transfer bits The SBI0CR1 BC2 0 is used to select a number of bits for next transmitting and receiving data Since the BC2 0 is cleared to 000 as a start condition a slave address and direction bit transmission are executed in 8 bits Other than these the BC2 0 retains a specified value 3 Serial clock a Clock source The SBI0CR1 SCK2 0 is used to select a maximum transfer frequency ...

Page 163: ...the high level Since master B holds the SCL line of the bus at the low level master A wait for counting high level width of an own clock pulse After master B finishes counting low level width of an own clock pulse at point c and master A detects the SCL line of the bus at the high level and starts counting high level of an own clock pulse The clock pulse on the bus is determined by the master devi...

Page 164: ...n generation When the SBI0SR BB is 0 slave address and direction bit which are set to SBI0DBR are output on a bus after generating a start condition by writing 1 to the SBI0CR2 MST TRX BB PIN It is necessary to set transmitted data to the data buffer register SBI0DBR and set 1 to ACK beforehand Figure 3 10 9 Start Condition Generation and Slave Address Generation When the BB is 1 a sequence of gen...

Page 165: ...onfirming a bus is free 10 Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2C bus mode a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data Data on the SDA line is used for I2C bus arbitration The following shows an example of a bus arbitration procedure when two master devices exist si...

Page 166: ...When I2C0AR ALS 1 SBI0SR AAS is set to 1 after the first word of data has been received SBI0SR AAS is cleared to 0 when data is written to or read from the data buffer register SBI0DBR 12 GENERAL CALL detection monitor SBI0SR AD0 is set to 1 in slave mode when a GENERAL CALL is received All 8 bit received data is 0 after a start condition SBI0SR AD0 is cleared to 0 when a start condition or stop c...

Page 167: ...y reading or writing the SBI0DBR In the master mode after the start condition is generated the slave address and the direction bit are set in this register 16 I2C bus address register I2C0AR I2C0AR SA6 0 is used to set the slave address when the TMP91C824 functions as a slave device The slave address output from the master device is recognized by setting the I2C0AR ALS to 0 The data format is the ...

Page 168: ...rom the slave device An INTSBI interrupt request occurs at the falling edge of the 9th clock The PIN is cleared to 0 In the master mode the SCL pin is pulled down to the low level while PIN is 0 When an interrupt request occurs the TRX is changed according to the direction bit only when an acknowledge signal is returned from the slave device b Slave mode In the slave mode the start condition and t...

Page 169: ...itted data to SBI0DBR When the next transmitted data is other than 8 bits set the BC 2 0 ACK and write the transmitted data to SBI0DBR After written the data PIN becomes 1 a serial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then the 1 word data is transmitted After the data is transmitted an INTSBI interrupt request occurs The PIN becomes 0 and the SCL line...

Page 170: ...e received The last data word does not generate a clock pulse as the acknowledge signal After the data has been transmitted and an interrupt request has been generated set BC 2 0 to 001 and read the data The TMP91C824 generates a clock pulse for a 1 bit data transfer Since the master device is a receiver the SDA line on the bus remains high The transmitter interprets the high signal as an ACK sign...

Page 171: ...the direction bit sent from another master is 1 1 0 In salve receiver mode the TMP91C824 receives a slave address for which the value of the direction bit sent from the master is 1 Set the number of bits a word in BC2 0 and write the transmitted data to SBI0DBR 1 0 0 0 In salve transmitter mode a single word of is transmitted Set BC 2 0 to the number of bits in a word Check the LRB setting If LRB ...

Page 172: ...dition when the other device has released the SCL line When SBI0CR2 MST TRX PIN are written 1 and BB is written 0 BB changes to 0 by internal SCL changes to 1 without waiting stop condition To check whether SCL and SDA pin are 1 by sensing their ports is needed to detect bus free condition Figure 3 10 17 Stop Condition Generation Single master Figure 3 10 18 Stop Condition Generation Multi master ...

Page 173: ...becomes 0 so as to ascertain when the TMP91C824 s SCL pin is released Check the LRB until it becomes 1 to check that the SCL line on a bus is not pulled down to the low level by other devices After confirming that the bus remains in a free state generate a start condition using the procedure described in 3 10 6 2 In order to satisfy the setup time requirements when restarting take at least 4 7 µs ...

Page 174: ...e 000 001 010 011 100 101 110 111 n 4 n 5 n 6 n 7 n 8 n 9 n 10 2 1 MHz 1031 3 kHz 515 6 kHz 257 8 kHz 128 9 kHz 64 5 kHz 32 2 kHz External mode System clock fc Clock gear fc 1 fc 33 MHz Output to SCK pin fscl Hz Input from SCK terminal Transfer mode selection 00 8 bit transmit mode 01 Reserved 10 8 bit transmit received mode 11 8 bit received mode Continue abort transfer 0 Continue transfer 1 Abor...

Page 175: ... C bus mode 11 Reserved Note 1 Set the SBI0CR1 BC2 0 000 before switching to a clocked synchronous 8 bit SIO mode Note 2 Please always write SBICR2 1 0 to 00 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Bit symbol SIOF SEF Read Write R After reset 0 0 Function Serial transfer operation status monitor Shift operation status monitor Shift operation status monitor 0 Shift operation terminated...

Page 176: ...p 1 Operate Operation in IDLE2 mode 0 Stop 1 Operate Serial Bus Interface Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4EN Read Write W W After reset 0 0 Function Internal clock 0 Stop 1 Operate Always write 0 Baud rate clock control 0 Stop 1 Operate Figure 3 10 22 Registers for the SIO Mode SBI0BR0 0244H SBI0BR1 0245H Prohibit read modify write Prohibit read modify write ...

Page 177: ...e serial clock and holds the next shift operation until reading or writing has been completed Figure 3 10 23 Automatic Wait Function External clock SCK2 0 111 An external clock input via the SCK pin is used as the serial clock In order to ensure the integrity of shift operations both the high and low level serial clock pulse widths shown below must be maintained The maximum data transfer frequency...

Page 178: ...nput output Trailing edge shift Data is shifted on the trailing edge of the serial clock on the rising edge of the SCK pin input output Figure 3 10 25 Shift Edge Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 76543210 7654321 765432 76543 7654 765 76 7 SO pin output 6543210 543210 0 10 210 3210 43210 76543210 SCK pin output Shift register SCK pin SI pin Shift register a Leading edge b Trailing edge Don t...

Page 179: ... data is written automatic wait function is canceled When the external clock is used data should be written to SBI0DBR before new data is shifted The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to SBI0DBR by the interrupt service program When the transmit is started after the SBI0SR SIOF goes 1 out...

Page 180: ... If SCK 0 then loop JR Z STEST2 LD SBI0CR1 00000111B SIOS 0 SBI0DBR INTSBI interrupt request SIOS SIOF SEF SCK pin Output SO pin b a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Clear SIOS a Write transmitted data a Internal clock SBI0DBR INTSBI interrupt request SIOS SIOF SEF SCK pin Input SO pin b a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Clear SIOS a Write transmitted data b External clo...

Page 181: ...is input If the received data is not read any further data which is to be received is canceled The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when the received data is read Receiving of data ends when SIOS is cleared to 0 by the buffer full interrupt service program or when SIOINH is set...

Page 182: ...ata is read and transmitted data is written before a new shift operation is executed The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time at which received data is read and transmitted data is written When the transmit is started after the SBI0SR SIOF goes 1 output from the SO pin holds final ...

Page 183: ...eceive SBI0DBR INTSBI interrupt request SIOS SIOF SEF SCK pin Output SO pin SI pin Clear SIOS c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 Write transmitted data a Read received data d a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 d b c a Read received data c Write transmitted data b Bit7 in last transmitted word SCK pin SIOF SO pin Bit6 tSODH Min 4 fFPH s ...

Page 184: ...tandby mode even though the internal comparator is still enabled Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed Figure 3 11 1 Block Diagram of AD Converter INTAD interrupt Comparator VREFH VREFL Multiplexer Sample and hold AD mode control register 1 ADMOD1 ADMOD1 ADTRGE ADCH2 0 VREFON Scan Repeat Interrupt Busy End Start Internal data bus C...

Page 185: ...Every conversion 1 Every fourth conversion Repeat mode specification 0 Single conversion 1 Repeat conversion mode Scan mode specification 0 Conversion channel fixed mode 1 Conversion channel scan mode AD conversion start 0 Don t care 1 Start conversion Always 0 when read AD conversion start 0 Don t care 1 Start AD conversion Note Always read as 0 AD scan mode setting 0 AD conversion channel fixed ...

Page 186: ...nned 000 AN0 AN0 001 AN1 AN0 AN1 010 AN2 AN0 AN1 AN2 011 Note AN3 AN0 AN1 AN2 AN3 100 AN4 AN4 101 AN5 AN4 AN5 110 AN6 AN4 AN5 AN6 111 AN7 AN4 AN5 AN6 AN7 AD conversion start control by external trigger ADTRG input 0 Disabled 1 Enabled IDLE2 control 0 Stopped 1 In operation Control of application of reference voltage to AD converter 0 OFF 1 ON Before starting conversion before writing 1 to ADMOD0 A...

Page 187: ... R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result AD conversion result flag 1 Conversion result stored AD Conversion Data Upper Register 1 5 7 6 5 4 3 2 1 0 Bit symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R After reset Undefined Function Stores upper 8 bits of AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel x conversion result 7 6 5 4 3 2 1 0 ...

Page 188: ... R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result AD Conversion Data Storage flag 1 conversion result stored AD Conversion Result Upper Register 3 7 7 6 5 4 3 2 1 0 Bit symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R After reset Undefined Function Stores upper 8 bits of AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel x conversion result 7 6 5 4 ...

Page 189: ...c then set ADMOD0 ADS to 1 2 Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter In analog input channel fixed mode ADMOD0 SCAN 0 Setting ADMOD1 ADCH2 0 selects one of the input pins AN0 to AN7 as the input channel In analog input channel scan mode ADMOD0 SCAN 1 Setting ADMOD1 ADCH2 0 selects one of the 8 scan modes Table 3 11 ...

Page 190: ...xed repeat conversion mode Channel scan repeat conversion mode The ADMOD0 REPEAT and ADMOD0 SCAN settings in AD mode control register 0 determine the AD mode setting Completion of AD conversion triggers an INTAD AD conversion end interrupt request Also ADMOD0 EOCF will be set to 1 to indicate that AD conversion has been completed a Channel fixed single conversion mode Setting ADMOD0 REPEAT and ADM...

Page 191: ... repeat conversion mode e g in cases c and d write a 0 to ADMOD0 REPEAT After the current conversion has been completed the repeat conversion mode terminates and ADMOD0 ADBF is cleared to 0 Switching to a halt state IDLE2 mode with ADMOD1 I2AD cleared to 0 IDLE1 mode or STOP mode immediately stops operation of the AD converter even when AD conversion is still in progress In repeat conversion modes...

Page 192: ... which are used to hold the results of AD conversion Table 3 11 3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel Port 8 Conversion Modes Other than at Right Channel Fixed Repeat Conversion Mode ITM0 1 AN0 ADREG04H L AN1 ADREG15H L AN2 ADREG26H L AN3 ADREG37H L AN4 ADREG04H L AN5 ADREG15H L AN6 ADREG26H L AN7 ADREG3...

Page 193: ...ersion mode Interrupt routine processing example WA ADREG37 Read value of ADREG37L and ADREG37H into 16 bit general purpose register WA WA 6 Shift contents read into WA six times to right and zero fill upper bits 0800H WA Write contents of WA to memory address 0800H b This example repeatedly converts the analog input voltages on the three pins AN0 AN1 and AN2 using channel scan repeat conversion m...

Page 194: ...necting the watchdog timer output to the reset pin internally forces a reset The level of external RESET pin is not changed 3 12 1 Configuration Figure 3 12 1 is a block diagram of he watchdog timer WDT Figure 3 12 1 Block Diagram of Watchdog Timer Note It needs to care designing the total machine set because watchdog timer can t operate completely by external noise Internal reset WDMOD WDTP1 0 WD...

Page 195: ...urs and the watchdog timer can reset device In this case the reset time will be between 22 and 29 states 21 3 28 1 µs at fOSCH 33MHz fFPH 2 2 MHz is fFPH 2 where fFPH is generated by diving the high speed oscillator clock fOSCH by sixteen through the clock gear function Figure 3 12 3 Reset Mode 0 WDT interrupt WDT clear Software Write clear code WDT counter n Overflow Overflow WDT counter n WDT in...

Page 196: ...e enabled state merely by setting WDTE to 1 c Watchdog timer out reset connection RESCR This register is used to connect the output of the watchdog timer with the RESET terminal internally Since WDMOD RESCR is initialized to 0 on reset a reset by the watchdog timer will not be performed 2 Watchdog timer control register WDCR This register is used to disable and clear the binary counter for the wat...

Page 197: ...2 control 0 Stop 1 Operation Watchdog timer detection time at fc 33 MHz fs 32 768 kHz Watchdog Timer Detection Time WDMOD WDTP1 0 SYSCR1 System Clock Selection SYSCK SYSCR1 Gear Value GEAR2 0 00 01 10 11 1 fs XXX 2 0 s 8 0 s 32 0 s 128 0 s 000 fc 1 99 ms 7 94 ms 31 78 ms 127 10 ms 001 fc 2 3 97 ms 15 89 ms 63 55 ms 254 20 ms 010 fc 4 7 94 ms 31 78 ms 127 10 ms 508 40 ms 011 fc 8 15 89 ms 63 55 ms ...

Page 198: ... 2 1 0 Bit symbol Read Write W After reset Function B1H WDT disable code 4EH WDT clear code B1H Disable code 4EH Clear code Others Don t care Figure 3 12 5 Watchdog Timer Control Register Disable clear WDT WDCR 0301H Prohibit read modify write ...

Page 199: ...INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti malfunction program The watchdog timer works immediately after reset The watchdog timer does not operate in IDLE1 or STOP mode as the binary counter continues counting during bus release when BUSAK goes low When the device is in IDLE2 mode the operation of WDT depends on the WDMOD I2WDT set...

Page 200: ...0 years In system to use it please manage upper two columns with the system side when handle year column in the Christian era Note 2 Leap year A leap year is the year which is divisible with 4 but the year which there is exception and is divisible with 100 is not a leap year However the year which is divisible with 400 is a leap year But there is not this product for the correspondence to the abov...

Page 201: ...1HZ enable 16HZ enable Clock reset Alarm reset Always write 0 Reset register Write only Note As for SECR MINR HOURR DAYR MONTHR YEARR of PAGE0 current state is read when read it Table 3 13 2 PAGE 1 Alarm function Registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read Write SECR 0320H R W MINR 0321H 40 min 20 min 10 min 8 min 4 min 2 min 1 min Minute column for alarm R W HOU...

Page 202: ...Function 0 is read 40 sec column 20 sec column 10 sec column 8 sec column 4 sec column 2 sec column 1 sec column 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 1 1 s 0 0 0 0 0 1 0 2 s 0 0 0 0 0 1 1 3 s 0 0 0 0 1 0 0 4 s 0 0 0 0 1 0 1 5 s 0 0 0 0 1 1 0 6 s 0 0 0 0 1 1 1 7 s 0 0 0 1 0 0 0 8 s 0 0 0 1 0 0 1 9 s 0 0 1 0 0 0 0 10 s 0 0 1 1 0 0 1 19 s 0 1 0 0 0 0 0 20 s 0 1 0 1 0 0 1 29 s 0 1 1 0 0 0 0 30 s 0 1 1 1 0 0 ...

Page 203: ... 1 min column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 m...

Page 204: ...clock 0 1 0 0 0 0 10 o clock 0 1 1 0 0 1 19 o clock 1 0 0 0 0 0 20 o clock 1 0 0 0 1 1 23 o clock Note Do not set the data other than showing above b In case of 12 hour clock mode MONTHR MO0 0 of PAGE1 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR 0322H Read Write R W After reset Undefined Function 0 is read PM AM 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 ...

Page 205: ...lumn register for PAGE0 1 7 6 5 4 3 2 1 0 Bit symbol DA5 DA4 DA3 DA2 DA1 DA0 DATER 0324H Read Write R W After reset Undefined Function 0 is read Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day 1 0 1 0 0 1 29th da...

Page 206: ...h 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Note Do not set the data other than showing above 7 Select 24 hour clock or 12 hour clock for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol MO0 MONTHR 0325H Read Write R W After reset Undefined Functi...

Page 207: ... 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 1 0 0 1 1 0 0 1 99 years Note Do not set the data other than showing above 9 Leap year register for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol LEAP1 LEAP0 Read Write R W After reset Undefined Function 0 is read 00 Leap year 01 One year after leap year 10 Two years after leap year 11 Three years after leap year 0 0 Current year is leap ye...

Page 208: ...sec counter become to 0 when the value of sec counter is 0 29 And in case that value of sec counter is 30 59 min counter is carried and become sec counter to 0 Output Adjust signal during 1 cycle of fSYS After being adjusted once Adjust is released automatically PAGE0 only 11 Reset register setting for PAGE0 1 7 6 5 4 3 2 1 0 Bit symbol DIS1Hz DIS16Hz RSTTMR RSTALM RE3 RE2 RE1 RE0 RESTR 1328H Read...

Page 209: ...data when carry of the inside counter happens during the operation which Clock data reads Therefore please read two times with the following way for reading correct data Figure 3 13 2 Flowchart of Clock Data Read Start PAGER PAGE 0 Select PAGE0 Read the clock data 1st Read the clock data 2nd 1st data 2nd data Yes No End ...

Page 210: ...by interrupt read clock data within 0 5s s after generating interrupt This is because count up of clock data occurs by rising edge of 1Hz pulse cycle Figure 3 13 3 Timing of INTRTC and Clock data 56 57 58 59 0 1 2 3 4 ALARM INTRTC 1s counter Internal signal 1s count UP Internal signal ...

Page 211: ...ase follow the below way 1 Reset for a divider Inside of RTC there is 15 stage divider which generates 1 Hz clock from 32 768 kHz Carry of a Clock is not done for 0 5 second when reset this divider So write in data during this interval Figure 3 13 4 Flowchart of Data Write Start PAGER PAGE 0 Select PAGE0 End Note This period is within 0 5 s Write the clock data RESTR RSTTMR 1 Divider reset ...

Page 212: ...hibited 1s carry hold circuit holds one second carry signal which is generated from divider After becoming clock enable state output the carry signal to clock and revise time and continue operation However clock is late when clock disabling state continues for one second or more Figure 3 13 5 Flowchart of Clock Disable Start Disable the clock End Enable the clock Write the clock data ...

Page 213: ...ng alarm min alarm hour alarm day and alarm the day week are done by writing in data at each register of PAGE1 When all setting contents accorded RTC generates INTRTC interrupt if PAGER INTENA ENAALM is 1 However contents don t care state which does not set it up is considered to always accord The contents which set it up once cannot be returned to don t care state in independence Initialization o...

Page 214: ... setting up PAGER ENAALM 0 RESTR DIS1HZ 0 DIS16HZ 1 And RTC generates INTRTC interrupt by falling edge of the clock 5 When output clock of 16 Hz RTC outputs clock of 16 Hz to ALARM pin by setting up PAGER ENAALM 0 RESTR DIS1HZ 1 DIS16HZ 0 And RTC generates INTRTC interrupt by falling edge of the clock ...

Page 215: ...MLDALM pin By connecting a loud speaker outside melody tone can sound easily Alarm generator The alarm function generates 8 kinds of alarm waveform having a modulation frequency 4096 Hz determined by the low speed clock 32 768 kHz And this waveform is able to invert by setting a value to a register By connecting a loud speaker outside alarm tone can sound easily And also 5 kinds of fixed cycle 1 H...

Page 216: ...kHz Stop clear Invert F F MELOUT Clear Reset Melody generator Edge detector INTALM0 8192 Hz INTALM1 512 Hz INTALM2 64 Hz INTALM3 2 Hz INTALM4 1 Hz 15 bit counter UC1 ALM resistor MELOUT ALMOUT Selector MLDALM pin Internal data bus Alarm wave form generator MELALMC FC1 0 Alarm generator Reset 4096 Hz Invert MELALMC MELALM MELALMC ALMINV ALMINT IALM4E 0E INTALMH Halt release 8 bit counter UC2 ...

Page 217: ...ead always 0 Note 2 When setting MELALMC register except FC1 0 during the free run counter is running FC1 0 is kept 01 MELFL Register 7 6 5 4 3 2 1 0 Bit symbol ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Setting melody frequency Lower 8 bits MELFH Register 7 6 5 4 3 2 1 0 Bit symbol MELON ML11 ML10 ML9 ML8 Read Write R W R W After reset 0 0 0 0 0 Function C...

Page 218: ...set to 12 bit register MELFH MELFL Followings are setting example and calculation of melody output frequency Formula for calculating of melody waveform frequency at fs 32 768 kHz melody output waveform fMLD Hz 32768 2 N 4 setting value for melody N 16384 fMLD 2 notice N 1 to 4095 001H to FFFH 0 is not acceptable Example program In case of outputting La musical scale 440 Hz LD MELALMC XXXX1B select...

Page 219: ... alarm waveform as output waveform from MLDALM Then 10 be set on MELALMC FC1 0 register and clear internal counter Finally alarm pattern has to be set on 8 bit register of ALM If it is inverted output data set ALMINV as invert Followings are example program setting value of alarm pattern and waveform of each setting value Setting value of alarm pattern Setting Value for ALM Register Alarm Waveform...

Page 220: ...ert 62 5 ms 62 5 ms 62 5 ms 62 5 ms 31 25 ms AL1 pattern Continuous output AL2 pattern 8 times 1 s 1 2 8 1 1 s 1 AL3 pattern once 500 ms AL4 pattern Twice 1 s 1 2 1 1 s 1 2 1 AL5 pattern 3 times 1 s 1 s 3 1 AL6 pattern once AL7 pattern Twice 1 2 AL8 pattern once 250 ms Modulation frequency 4096 Hz ...

Page 221: ...r an instant Any one of the ratings must not be exceeded If any absolute maximum rating is exceeded a device may break down or its performance may be degraded causing it to catch fire or explode resulting in injury to the user Thus when designing products which include this device ensure that no absolute maximum rating value will ever be exceeded Solderability of lead free products Test parameter ...

Page 222: ... 7V 0 3 Vcc 2 7V 0 2 Vcc Input low voltage X1 VIL4 Vcc 2 7V 0 3 0 1 Vcc 3 6V Vcc 3 3V 2 4 3 3V Vcc 2 7V 2 0 D0 to D15 VIH Vcc 2 7V 0 7 Vcc Vcc 2 7V 0 7 Vcc P52 to PD7 Except PB3 VIH1 Vcc 2 7V 0 8 Vcc Vcc 2 7V 0 75 Vcc RESET NMI PB3 INT0 VIH2 Vcc 2 7V 0 85 Vcc Vcc 2 7V Vcc 0 3 AM0 to AM1 VIH3 Vcc 2 7V Vcc 0 3 Vcc 2 7V 0 8 Vcc Input high voltage X1 VIH4 Vcc 2 7V 0 9 Vcc Vcc 0 3 V IOL 1 6 mA Vcc 2 7V...

Page 223: ...2 7 V 80 400 Programmable pull up resistor RKH Vcc 2 V 10 200 1000 kΩ NORMAL Note 2 14 0 20 0 IDLE2 4 0 6 1 IDLE1 3 6 V Vcc 2 7 V fc 33 MHz 1 2 2 2 NORMAL Note 2 2 6 3 0 IDLE2 0 7 1 2 IDLE1 Vcc 2 V 10 fc 10 MHz Typ Vcc 2 0 V 0 2 0 4 mA SLOW Note 2 17 5 30 5 IDLE2 7 0 13 5 IDLE1 3 6 V Vcc 2 7 V fs 32 768 kHz 5 0 10 0 SLOW Note 2 10 5 13 0 IDLE2 4 5 6 5 IDLE1 Vcc 2 V 10 fs 32 768 kHz Typ Vcc 2 0 V 3...

Page 224: ...x 15 45 ns 10 D0 to D15 valid WR rise tDW 1 5x 35 10 ns 11 WR rise D0 to D15 hold tWD x 25 5 ns 12 A0 to A23 valid WAIT input tAW 3 5x 60 46 ns 13 RD WR fall WAIT hold tCW 2 5x 0 76 ns 14 A0 to A23 valid Port input tAPH 3 5x 89 17 ns 15 A0 to A23 valid Port hold tAPH2 3 5x 106 ns 16 A0 to A23 valid Port valid tAPO 3 5x 60 166 ns AC measuring conditions Output level High 0 7 Vcc Low 0 3 Vcc CL 50 p...

Page 225: ... D0 to D15 valid WR rise tDW 1 5x 70 80 ns 11 WR rise D0 to D15 Hold tWD x 50 50 ns 12 A0 to A23 valid WAIT input tAW 3 5x 120 230 ns 13 RD WR fall WAIT hold tCW 2 5x 0 250 ns 14 A0 to A23 valid Port input tAPH 3 5x 50 300 ns 15 A0 to A23 valid Port hold tAPH2 3 5x 350 ns 16 A0 to A23 valid Port valid tAPO 3 5x 60 410 ns AC measuring conditions Output level High 0 7 V Low 0 3 V CL 50 pF Input leve...

Page 226: ...Therefore the above waveform diagram should be regarded as depicting internal operation Please also note that the timing and AC characteristics of port input output shown above are typical representation For details contact your local Toshiba sales representative tHR fFPH EA24 EA25 A23 to A0 R W Port input Note RD D0 to D15 tFPH tAW tAP tAD tAC tRR tCAR D0 to D15 tCW tAPH2 CSn WAIT tRD ...

Page 227: ...ot enabled Therefore the above waveform diagram should be regarded as depicting internal operation Please also note that the timing and AC characteristics of port input output shown above are typical representation For details contact your local Toshiba sales representative D0 to D15 tWD tAPO tWW tDW fFPH EA24 EA25 A23 to A0 R W Port output Note D0 to D15 WAIT WR HWR CSn tCAW ...

Page 228: ...EFL VCC 2 V 10 VSS Vss Vss Analog input voltage range VAIN VREFL VREFH V 3 6 V VCC 2 7 V 0 94 1 35 Analog current for analog reference voltage VREFON 1 VCC 2 V 10 0 65 0 90 mA VREFON 0 IREF VREFL 0 V 3 6 V VCC 2 7 V 0 02 5 0 µA 3 6 V VCC 2 7 V 1 0 4 0 Error Not including quantizing errors VCC 2 V 10 1 0 4 0 LSB Note 1 1 LSB VREFH VREFL 1024 V Note 2 The operation above is guaranteed for fFPH 4 MHz...

Page 229: ...ing edge tRDS 0 0 0 ns Note SCLK rising falling edge The rising edge is used in SCLK rising mode The falling edge is used in SCLK falling mode 2 SCLK output mode Variable 10 MHz 27 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK period tSCY 16X 8192X 1 6 819 0 59 303 µs Output data SCLK rising falling edge tOSS tSCY 2 40 760 256 ns SCLK rising falling edge Output data hold tOHS tSCY 2 40 76...

Page 230: ...e 10 MHz 27 MHz Parameter Symbol Min Max Min Max Min Max Unit NMI INT0 to INT3 low level width tINTAL 4X 40 440 188 ns NMI INT0 to INT3 high level width tINTAH 4X 40 440 188 ns 4 8 SCOUT Pin AC Characteristics Variable 10MHz 27 MHz Parameter Symbol Min Max Min Max Min Max Condition Unit 0 5T 10 90 27 Vcc 2 7 V Low level width tSCH 0 5T 30 70 Vcc 2 7 V ns 0 5T 10 90 27 Vcc 2 7 V High level width tS...

Page 231: ...2 This line shows only that the output buffer is in the off state It does not indicate that the signal level is fixed Just after the bus is released the signal level set before the bus was released is maintained dynamically by the external capacitance Therefore to fix the signal level using an external resister during bus release careful design is necessary since fixing of the level is delayed The...

Page 232: ...tor is sum of external loads C1 and C2 and floating loads of actual assemble board There is a possibility of miss operating using C1 and C2 value in below table When designing board it should design minimum length pattern around oscillator And we recommend that oscillator evaluation try on your actual using board 1 Connection example Low frequency oscillator High frequency oscillator XT1 XT2 C1 C2...

Page 233: ...scillator C1 pF C2 pF Rf Ω Rd Ω Voltage of Power V Tc C 4 00 CSTS0400MG06 CSTLS4M00G56 B0 47 47 Open 0 6 750 CSTS0675MG06 CSTLS6M75G56 B0 47 47 Open 0 CSA12 5MTZ CSALA12M5T55 B0 30 30 Open 0 12 50 CST12 0MTW CSTLA12M5T55 B0 30 30 Open 0 CSALS20M0X53 B0 5 5 Open 0 20 00 CSTLS20M0X51 B0 5 5 Open 0 27 00 CSALS27M0X51 B0 Open Open 10k 0 TMP91C824 32 00 CSALA32M0X51 B0 3 3 Open 0 2 7 to 3 6 40 to 85 NO...

Page 234: ...ns on these register Example When setting bit0 only of the register PxCR the instruction SET 0 PxCR cannot be used The LD Transfer instruction must be used to write all eight bits Read Write R W Both read and write are possible R Only read is possible W Only write is possible W Both read and write are possible when this bit is read as 1 Prohibit RMW Read modify write instructions are prohibited Th...

Page 235: ...TE12 2H 2H DMA2V 2H INTE3ALM4 3H 3H DMA3V 3H INTEALM01 4H 4H 4H INTEALM23 5H 5H 5H INTETA01 6H 6H 6H INTETA23 7H 7H 7H INTERTC 8H 8H INTCLR 8H INTES0 9H 9H DMAR 9H INTES1 AH AH DMAB AH INTES2 BH BH BH INTETC01 CH CH IIMC CH INTETC23 DH PZ DH DH INTEP01 EH PZCR EH EH FH PZFC FH FH 4 CS WAIT 5 6 CGEAR DFM Address Name Address Name 00C0H B0CS 00E0H SYSCR0 1H B1CS 1H SYSCR1 2H B2CS 2H SYSCR2 3H B3CS 3...

Page 236: ...D0 2H I2C0AR 3H BR0CR 3H SBI0CR2 SBI0SR 4H BR0ADD 4H SBI0BR0 5H SC0MOD1 5H SBI0BR1 6H 6H 7H SIRCR 7H 8H SC1BUF 8H 9H SC1CR 9H AH SC1MOD0 AH BH BR1CR BH CH BR1ADD CH DH SC1MOD1 DH EH EH FH FH 10 10 bit ADC Address Name Address Name 02A0H ADREG04L 02B0H ADMOD0 1H ADREG04H 1H ADMOD1 2H ADREG15L 2H 3H ADREG15H 3H 4H ADREG26L 4H 5H ADREG26H 5H 6H ADREG37L 6H 7H ADREG37H 7H 8H 8H 9H 9H AH AH BH BH CH CH...

Page 237: ...ONTHR 6H 6H YEARR 7H 7H PAGER 8H 8H RESTR 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH 13 MLD 14 MMU Address Name Address Name 0330H ALM 0350H LOCAL0 1H MELALMC 1H LOCAL1 2H MELFL 2H LOCAL2 3H MELFH 3H LOCAL3 4H ALMINT 4H 5H 5H 6H 6H 7H 7H 8H 8H 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH Note Do not access to the unnamed addresses e g addresses to which no register has been allocated ...

Page 238: ...1 1 1 1 0 1 1 P72 P71 P70 R W Data from external port Output latch register is set to 1 P7 Port 7 13H 0 Output latch register Pull up resistor OFF 1 Output latch register Pull up resistor ON P87 P86 P85 P84 P83 P82 P81 P80 R P8 Port 8 18H Data from external port PB6 PB5 PB4 PB3 PB2 PB1 PB0 R W PB Port B 22H Data from external port Output latch register is set to 1 PC5 PC4 PC3 PC2 PC1 PC0 R W PC Po...

Page 239: ...RQ P65F P64F P63F P62F P61F P60F W W W 0 0 0 0 0 0 0 0 P6FC Port 6 function 15H Prohibit RMW Always write 0 0 Port 1 EA25 0 Port 1 EA24 0 Port 1 CS3 0 Port 1 CS2 0 Port 1 CS1 0 Port 1 CS0 P67F2 P66F2 P65F2 P64F2 P62F2 W W W W W 0 0 0 0 0 0 0 0 P6FC2 Port 6 function 2 1BH Prohibit RMW 0 P67F 1 CS2E 0 P66F 1 CS2D 0 P65F 1 CS2C 0 P64F 1 CS2B Always write 0 0 P62F 1 CS2A Always write 0 P72C P71C P70C ...

Page 240: ...1 TA3OUT 0 Port 1 TA1OUT PC5C PC4C PC3C PC2C PC1C PC0C W 0 0 0 0 0 0 PCCR Port C control 26H Prohibit RMW 0 Input 1 Output PC5F PC3F PC2F PC0F W W W W 0 0 0 0 PCFC Port C function 27H Prohibit RMW 0 Port 1 SCLK1 0 Port 1 TXD1 0 Port 1 SCLK0 0 Port 1 TXD0 ODEPC3 ODEPC0 W W 0 0 PCODE Port C open drain 28H Prohibit RMW 0 CMOS 1 Open drain 0 CMOS 1 Open drain PD7F PD6F PD5F W W W 0 0 0 PDFC Port D fun...

Page 241: ...C IA0M2 IA0M1 IA0M0 R R W R R W 0 0 0 0 0 0 0 0 INTEALM01 INTALM 0 and INTALM 1 enable 93H 1 INTALM1 Interrupt level 1 INTALM0 Interrupt level INTALM3 INTALM2 IA3C IA3M2 IA3M1 IA3M0 IA2C IA2M2 IA2M1 IA2M0 R R W R R W 0 0 0 0 0 0 0 0 INTEALM23 INTALM2 and INTALM3 enable 94H 1 INTALM3 Interrupt level 1 INTALM2 Interrupt level INTTA1 TMRA1 INTTA0 TMRA0 ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 I...

Page 242: ...NTTX1 and INTTRX1 enable 99H 1 INTTX1 Interrupt level 1 INTRX1 Interrupt level INTSBI ISBIC ISBIM2 ISBIM1 ISBIM0 R R W 0 0 0 0 INTES2 INTESBI enable 9AH Always write 0 1 INTSBI Interrupt level INTTC1 INTTC0 ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R W R R W INTETC01 INTTC0 and INTTC1 enable 9BH 0 0 0 0 0 0 0 0 INTTC3 INTTC2 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R W...

Page 243: ...CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0 W 0 0 0 0 0 0 INTCLR Interrupt clear control 88H Prohibit RMW Clears interrupt request flag by writing to DMA start vector DMAR3 DMAR2 DMAR1 DMAR0 R W R W R W R W 0 0 0 0 DMAR DMA software request register 89H Prohibit RMW 1 DMA request in software DMAB3 DMAB2 DMAB1 DMAB0 R W R W R W R W 0 0 0 0 DMAB DMA burst request register 8AH 1 DMA request on burst mode I3E...

Page 244: ...aits 100 Reserved 001 1 wait 101 3 waits 010 1 N waits 110 4 waits 011 0 waits 111 8 waits B3E B3OM1 B3OM0 B3BUS B3W2 B3W1 B3W0 W W W W W W W 0 0 0 0 0 0 0 B3CS Block 3 CS WAIT control register C3H Prohibit RMW 0 Disable 1 Enable 00 ROM SRAM 01 10 Reserved 11 Data bus width 0 16 bits 1 8 bits 000 2 waits 100 Reserved 001 1 wait 101 3 waits 010 1 N waits 110 4 waits 011 0 waits 111 8 waits BEXBUS B...

Page 245: ...s A23 to A16 V22 V21 V20 V19 V18 V17 V16 V15 R W 1 1 1 1 1 1 1 1 MAMR2 Memory address mask register 2 CDH CS2 area size 0 Enable to address comparison S23 S22 S21 S20 S19 S18 S17 S16 R W 1 1 1 1 1 1 1 1 MSAR3 Memory start address register 3 CEH Start address A23 to A16 V22 V21 V20 V19 V18 V17 V16 V15 R W 1 1 1 1 1 1 1 1 MAMR3 Memory address mask register 3 CFH CS3 area size 0 Enable to address com...

Page 246: ...Warm up timer 0 write Don t care 1 write Start timer 0 read End warm up 1 read Not end warm up Select prescaler clock 00 fFPH 01 Reserved 10 fc 16 11 Reserved SYSCK GEAR2 GEAR1 GEAR0 R W 0 1 0 0 SYSCR1 System clock control register 1 E1H System clock selection 0 fc 1 fs Note 2 High frequency gear value selection fc 000 fc 001 fc 2 010 fc 4 011 fc 8 100 fc 16 101 Reserved 110 Reserved 111 Reserved ...

Page 247: ...egister 1 E4H EMCCR2 EMC control register 2 E5H Switching the protect ON OFF by write to following 1st KEY and 2nd KEY 1st KEY EMCCR1 5AH EMCCR2 A5H in succession write 2nd KEY EMCCR1 A5H EMCCR2 5AH in succession write ENFROM ENDROM ENPROM FFLAG DFLAG PFLAG R W R W R W R W R W R W 0 0 0 0 0 0 CS1A Write operation flag CS2B 2G Write operation flag CS2A Write operation flag EMCCR3 EMC control regist...

Page 248: ... RUN fOSCH 10 RUN STOP fDFM DFMCR0 DFM control register 0 E8H 11 RUN STOP fOSCH Lockup flag 0 End LUP 1 Do not Lockup time 0 212 fOSCH 1 210 fOSCH D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W 0 0 0 1 0 0 1 1 DFMCR1 DFM control register 1 E9H DFM correction Input frequency 4 to 8 25 MHz at 2 7 to 3 6 V Write 0BH Input frequency 2 to 2 5 MHz at 2 0V 10 Write 1BH ...

Page 249: ...trol 105H Prohibit RMW 00 Invert TA1FF 01 Set TA1FF 10 Clear TA1FF 11 Don t care 1 TA1FF enable 0 TMRA0 1 TMRA1 inversion 7 2 TMRA23 Symbol Name Address 7 6 5 4 3 2 1 0 TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN R W R W R W R W R W 0 0 0 0 0 TA23RUN 8 bit timer RUN register 108H Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 8 bit timer run stop control 0 Stop and clear 1 Run Count up W TA2REG ...

Page 250: ...11 UART 9 bits 00 TA0TRG 01 Baud rate 10 Internal clock fSYS 11 External clock BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R W 0 0 0 0 0 0 0 BR0CR Baud rate control 203H Always write 0 1 16 K 16 divided 00 φT0 01 φT2 10 φT8 11 φT32 Setting the divided frequency N 0 to F BR0K3 BR0K2 BR0K1 BR0K0 R W 0 0 0 0 BR0ADD Serial channel 0 K setting register 204H Sets the frequency divisor K Divided by N 1...

Page 251: ...RXE WU SM1 SM0 SC1 SC0 R W 0 0 0 0 0 0 0 0 SC1MOD0 Serial channel 1 mode 20AH Transmission data bit8 1 CTS enable 1 Receive enable 1 Wakeup 00 I O interface 01 UART 7 bits 10 UART 8 bits 11 UART 9 bits 00 TA0TRG 01 Baud rate generator 10 Internal clock fSYS 11 External clock SCLK1 BR1ADDE BR1CK1 BR1CK BR1S3 BR1S2 BR1S1 BR1S0 R W 0 0 0 0 0 0 0 0 BR1CR Baud rate control 20BH Always write 0 1 16 K 16...

Page 252: ... 1 0 0 0 0 When read SBI0SR Serial bus interface status register Bus status monitor 0 Free 1 Busy Arbitration lost detection monitor 1 Detect Slave address match detection monitor 1 Detect GENERAL CALL detection monitor 1 Detect Lost receive bit monitor 0 0 1 1 When write SBI0CR2 Serial bus interface control register 2 243H I2 C bus mode Prohibit RMW 0 Slave 1 Master 0 Receiver 1 Transmit Start st...

Page 253: ...2 AN0 AN1 AN2 011 AN3 AN0 AN1 AN2 AN3 100 AN4 AN4 101 AN5 AN4 AN5 110 AN6 AN4 AN5 AN6 111 AN7 AN4 AN5 AN6 AN7 ADR01 ADR00 ADR0RF R R ADREG04L AD result register 0 4 low 2A0H Undefined 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R ADREG04H AD result register 0 4 high 2A1H Undefined ADR11 ADR10 ADR1RF R R ADREG15L AD result register 1 5 low 2A2H Undefined 0 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ...

Page 254: ...4 3 2 1 0 WDTE WDTP1 WDTP0 I2WDT RESCR R W R W R W R W R W R W 1 0 0 0 0 0 WDMOD WDT mode register 300H 1 WDT enable 00 215 fSYS 01 217 fSYS 10 219 fSYS 11 221 fSYS IDLE2 0 Abort 1 Operate 1 RESET Always write 0 W WDCR WDT control 301H Prohibit RMW B1H WDT disable 4EH WDT clear ...

Page 255: ...s 2 days 1 day MO4 MO3 MO2 MO1 MO0 R W 325H Undefined Page 0 0 is read 10 month 8 month 4 month 2 month 1 month MONTHR Month register Page 1 0 is read 0 Indicator for 1 Indicator for YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 R W 326H Undefined Page 0 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year YEARR Year register Page 1 0 is read Leap year setting INTENA Adjust ENATMR ENAALM PAGE R W ...

Page 256: ...10 Clear 11 Clear and start Alarm frequency invert 1 Invert Always write 0 Output frequency 0 Alarm 1 Melody ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 R W 0 0 0 0 0 0 0 0 MELFL Melody frequency register L 332H Melody frequency set Low 8 bits MELON ML11 ML10 ML9 ML8 R W R W 0 0 0 0 0 MELFH Melody frequency register H 333H Melody counter control 0 Stop and clear 1 Start Melody frequency set High 4 bits IALM4E...

Page 257: ...BANK for LOCAL1 0 Disable 1 Enable LOCAL1 area ANK set 001 setting is prohibited because it pretend COMMON 0 area L2E L2EA23 L2EA22 L2EA21 R W R W 0 0 0 0 LOCAL2 LOCAL2 control register 352H BANK for LOCAL2 0 Disable 1 Enable LOCAL2 area BANK set 111 setting is prohibited because it pretend COMMON 0 area L3E L3EA26 L3EA25 L3EA24 L3EA23 L3EA22 R W R W 0 0 0 0 0 0 LOCAL3 LOCAL3 control register 353H...

Page 258: ...modify write instructions on the TLCS 900 Exchange instruction EX mem R Arithmetic operations ADD mem R ADC mem R SUB mem R SBC mem R INC 3 mem DEC 3 mem Logic operations AND mem R OR mem R XOR mem R Bit manipulation operations STCF 3 A mem RES 3 mem SET 3 mem CHG 3 mem TSET 3 mem Rotate and shift operations RLC mem RRC mem RL mem RR mem SLA mem SRA mem SLL mem SRL mem RLD mem RRD mem c fc fs fFPH...

Page 259: ...ll up pull down resistors ON OFF Consequently read modify write instructions are prohibited g Bus release function It is described note point in 3 5 Port Function that pin s conditions at bus release condition Please refer that h Watchdog timer The watchdog timer starts operation immediately after a reset is released When the watchdog timer is not to be used disable it When the bus is released nei...

Page 260: ...iod CPU is shifting to the HALT mode for about 5 clocks of fFPH with IDLE1 or STOP mode IDLE2 is not applicable to this case In this case an interrupt request is kept on hold internally If another interrupt is generated after it has shifted to HALT mode completely halt status can be released without difficulty The priority of this interrupt is compared with that of the interrupt kept on hold inter...

Page 261: ...TMP91C824 91C824 259 2008 02 20 7 Package Dimensions LQFP100 P 1414 0 50F Unit mm ...

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