TMP91C824
91C824-21
2008-02-20
(2)
Clock gear controller
When the high-frequency clock fc is selected by setting SYSCR1<SYSCK>
=
0, f
FPH
is set according to the contents of the clock gear select register SYSCR1<GEAR0:2> to
either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
FPH
reduces power consumption.
Example 3:
Changing to a high-frequency gear
SYSCR1 EQU 00E1H
LD
(SYSCR1),XXXX0000B
; Changes f
SYS
to fc/2.
X: Don’t care
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2:0>
register. It is necessary the warm-up time until changing after writing the register
value.
There is the possibility that the instruction next to the clock gear changing
instruction is executed by the clock gear before changing. To execute the instruction
next to the clock gear switching instruction by the clock gear after changing, input
the dummy instruction as follows (Instruction to execute the write cycle).
Example:
SYSCR1 EQU 00E1H
LD
(SYSCR1),XXXX0001B
; Changes f
SYS
to fc/4.
LD
(DUMMY), 00H
; Dummy instruction
Instruction to be executed after clock gear has changed
(3)
Internal clock terminal out function
It can out internal clock (f
SYS
or fs) from PD5/SCOUT.
PD5 pin function is set to SCOUT output by the following bit setting.
: PDFC<PD5F>
=
1
Output clock select
: Refer to SYSCR2<SCOSEL> bit setting
HALT Mode
HALT Mode
SCOUT Select
NORMAL
SLOW
IDLE2 IDLE1 STOP
<SCOSEL>
=
0
fs clock out
<SCOSEL>
=
1
f
SYS
clock out
0 or 1 fix out
