THORLABS CLD101 Series, Operation Manual

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CLD101x
Status Byte Register
The Status Byte Register gives a summary of all underlying status structures. See also IEEE488.2-
1992-§11.2.
Bit # Mnemonic Description
7 OPER Standard Operation Status Structure Summary Bit
6 RQS/MSS Request Service / Master Summary Status
5 ESB Standard Event Status Bit
4 MAV Message Available. There is response data available for readout
3 QUES Questionable Status Structure Summary Bit
2 EAV Error Available. There is at least one error in the error queue.
1 MEAS Measurement Status Structure Summary Bit
0 reserved, read as 0
Standard Event Status Structure
The Standard Event Status Structure is described in IEEE488.2-1992-§11.5.
Standard Operation Register
The Standard Operation Status Structure is described in SCPI1999.0-Vol1-§9.3. In addition bit
8..12 are used as output state/on indicators.
Bit # Mnemonic Description
15..13 See SCPI1999.0-Vol1-§9.3
12 TECON TEC output is currently ON
11 LDON LD output is currently ON
10 TECST TEC output state is ON
9 LDST LD output state is ON
8 reserved, read as 0
7..0 See SCPI1999.0-Vol1-§9.3
Questionable Data Register
The Questionable Data Status Structure is described in SCPI1999.0 Vol1 §9.4.
Measurement Status Register
The Measurement Status Register Status Byte Register reports device operation and
measurement states.
Bit # Description
15 reserved, read as 0
14 Over temperature (Instrument is too hot)