THCV242_ Rev.2.00_E
Copyright
©
2019 THine Electronics, Inc. THine Electronics, Inc.
19/53
Security E
In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial access
and Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x0042 bit0) selects whether 2-wire serial slave of Sub-
Link Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register access
or remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.
Figure 8.
Sub-Link Master 2-wire slave clock stretching operation
2-wire Write
A
...
SD1
(SCL)
SD0
(SDA)
Access start to Sub-Link Slave
’
s register or
Remote side 2-wire serial Slave
’
s register
...
Stop
Condition
2-wire Write
A
...
SD1
(SCL)
SD0
(SDA)
Access start to Sub-Link Slave
’
s register or
Remote side 2-wire serial Slave
’
s register
...
Stop
Condition
Clock Stretching
INT
Interruption
R_2WIRE_CLKSEN=1 (Clock Stretching Enable)
R_2WIRE_CLKSEN=0 (No Clock Stretching)
Sub-Link communication time + Sub-Link Slave side internal bus access process time
or
Sub-Link communication time + Remote side 2-wire serial Access Time
Sub-Link Slave register Access or
Remote side 2-wire serial register
Access completion
