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THine THCV242 Manual Download Page 16

 

THCV242_ Rev.2.00_E 

Copyright

©

2019 THine Electronics, Inc.                                                                                                        THine Electronics, Inc. 

16/53 

Security E 

  2-wire serial I/F Watch Dog Timer 

2-wire Watch Dog Timer (WDT) is installed to monitor status. 

 

Table 9.

 

2-wire WDT setting 

 

 

 

 

 

 

Addr(h)

bit

Register Name

width

R/W

Description

Default

0x003B

[7:5] reserved

3

-

-

-

[4]

R_2WIRE_WD_EN

1

RW

2WIRE WDT Enable
0:Disable
1:Enable

1'b1

[3:1] reserved

3

-

-

-

[0]

R_2WIRE_WD_OFFSET

1

RW

2WIRE_WDT_OffsetTime
1:11'd2047
0:11'd1023

1'd1

0x003C

[7:0] R_2WIRE_WD_TIM

8

RW 2WIRE WDT_time=64×{R_2WIRE_WD_TIM<7:0>+1}×{2WIRE_WDT_OffsetTime}×tOSC

8'd255

Summary of Contents for THCV242

Page 1: ...ial interface Several fault and error detection function including CRC provides hardware functional safety design 2 Features MIPI CSI 2 with 1 2 or 4 lane output MIPI D PHY supports 80Mbps 1 2Gbps MIPI Virtual channel supported Video formats RAW8 10 12 14 16 20 YUV422 420 RGB888 666 565 JPEG User defined generic 8 bit V by One HS 400Mbps 4Gbps x2lane V by One HS standard version1 5 Video stream sw...

Page 2: ... Register 15 2 wire serial I F Watch Dog Timer 16 Sub Link setting 17 Sub Link 2 wire Read Write access to remote Register 18 6 3 5 1 Sub Link 2 wire Set and Trigger mode 18 6 3 5 2 Sub Link 2 wire Pass Through mode 21 Sub Link transaction time accuracy Improvement 24 6 4 GPIO setting 25 Register GPIO 26 Through GPIO 27 GPIO as secondary 2 wire port 28 6 5 MIPI 29 Deserializer and CSI 2 Formatter ...

Page 3: ...ent 47 10 DC Specifications 48 10 1 CMOS DC Specifications 48 10 2 CML Receiver DC Specifications 48 10 3 MIPI Transmitter DC Specifications 49 10 4 CML Bi directional Buffer DC Specifications 50 11 AC Specifications 51 11 1 General AC Specifications 51 11 2 CML Receiver AC Specifications 51 11 3 MIPI Transmitter AC Specifications 51 11 4 CML B directional Buffer AC Specifications 51 11 5 2 wire s...

Page 4: ...XTSYNC ERR1 50 31 PDN VDDCORE 51 30 VDDPLL VDDRX 52 29 VDDTX RX0N 53 28 MTX3P RX0P 54 27 MTX3N VSSRX 55 26 MTX1P RX1N 56 25 MTX1N RX1P 57 24 MTXCLK0P VDDRX 58 23 MTXCLK0N RSVDL0 59 22 MTX0P RSVDL0 60 21 MTX0N VSSRX 61 20 MTX2P RSVDL0 62 19 MTX2N RSVDL0 63 18 MTXCLK1P VDDRX 64 17 MTXCLK1N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDDCORE VDDIO2 RCM0N RCM0P RCM1N RCM1P RSVDL2 RSVDL2 RSVDL2 RSVDL2 VDDIO...

Page 5: ... 44 B General Purpose Input Output GPIO5 45 B General Purpose Input Output GPIO6 46 B General Purpose Input Output GPIO7 47 B General Purpose Input Output INT0 38 O INT1 39 O ERR0 49 O Internal Error status signal monitoring output ERR1 50 O Internal Error status signal monitoring output EXTSYNC 32 B External Sync input output for multiple camera syncronization RSVDL0 59 60 62 63 I0 Reserved Pins ...

Page 6: ... setting Setting of V by One HS input format can be configurable by 2 wire access to internal register Table 1 V by One HS input format setting bit Register Name width R W init Description 0x10 10 7 6 R_MLNK_NHSEL0 2 R W 2 h2 V by One Main Link Mode Select for LINK0 00 Reserved 01 Reserved 10 V by One HS standard mode 11 Reserved 0x10 10 5 4 R_MLNK_COL0 2 R W 2 h1 V by One Main Link Byte Mode Sele...

Page 7: ...transmitter must have installed MPRF format decoder like THCV241 because MPRF is not standard format Input V by One HS Byte Mode is 4Byte Mode Video formats RAW8 10 12 14 16 20 YUV422 420 RGB888 666 565 JPEG and User defined generic 8 bit are all supported with MPRF Figure 1 MPRF Main Link PRivate Format THCV241 CMOS Sensor THCV242 Processor In ECU or controller Original Data packet format payload...

Page 8: ... 7 Cb 7 Y 7 1st pixel V by One HS_D 22 B 6 0 Cb 6 Cr 6 Y 6 Cb 6 Y 6 1st pixel V by One HS_D 21 B 5 0 Cb 5 Cr 5 Y 5 Cb 5 Y 5 1st pixel V by One HS_D 20 B 4 0 Cb 4 Cr 4 Y 4 Cb 4 Y 4 1st pixel V by One HS_D 19 B 3 0 Cb 3 Cr 3 Y 3 Cb 3 Y 3 1st pixel V by One HS_D 18 B 2 0 Cb 2 Cr 2 Y 2 Cb 2 Y 2 1st pixel V by One HS_D 17 B 1 0 Cb 1 Cr 1 Y 1 Cb 1 Y 1 1st pixel V by One HS_D 16 B 0 0 Cb 0 Cr 0 Y 0 Cb 0 ...

Page 9: ... V by One HS_D 17 0 RAW 1 1st pixel RAW 1 1st pixel V by One HS_D 16 0 RAW 0 1st pixel RAW 0 1st pixel V by One HS_D 15 RAW 7 2nd pixel 0 RAW 7 4th pixel V by One HS_D 14 RAW 6 2nd pixel 0 RAW 6 4th pixel V by One HS_D 13 RAW 5 2nd pixel 0 RAW 5 4th pixel V by One HS_D 12 RAW 4 2nd pixel 0 RAW 4 4th pixel V by One HS_D 11 RAW 3 2nd pixel 0 RAW 3 4th pixel V by One HS_D 10 RAW 2 2nd pixel 0 RAW 2 4...

Page 10: ...0 RAW 4 1st pixel RAW 8 1st pixel V by One HS_D 17 0 RAW 3 1st pixel RAW 7 1st pixel V by One HS_D 16 0 RAW 2 1st pixel RAW 6 1st pixel V by One HS_D 15 0 0 RAW 5 1st pixel V by One HS_D 14 0 0 RAW 4 1st pixel V by One HS_D 13 0 0 RAW 3 1st pixel V by One HS_D 12 0 0 RAW 2 1st pixel V by One HS_D 11 0 0 0 V by One HS_D 10 0 0 0 V by One HS_D 9 RAW 1 RAW 1 2nd pixel RAW 1 2nd pixel V by One HS_D 8 ...

Page 11: ...6 1st pixel RAW 10 1st pixel V by One HS_D 17 0 RAW 5 1st pixel RAW 9 1st pixel V by One HS_D 16 0 RAW 4 1st pixel RAW 8 1st pixel V by One HS_D 15 0 0 RAW 7 1st pixel V by One HS_D 14 0 0 RAW 6 1st pixel V by One HS_D 13 0 0 RAW 5 1st pixel V by One HS_D 12 0 0 RAW 4 1st pixel V by One HS_D 11 RAW 3 RAW 3 2nd pixel RAW 3 2nd pixel V by One HS_D 10 RAW 2 RAW 2 2nd pixel RAW 2 2nd pixel V by One HS...

Page 12: ... Link is in lock status or not LOCKN at Transmitter input is set to High by pull up resistor when Receiver is not active or in CDR PLL training LOCKN is set to Low by Receiver when CDR lock is completed After that the CDR training mode finishes and then Transmitter shifts to the normal mode LOCKN of Receiver is open drain Transmitter side needs pull up resistor When an application omits HTPDN LOCK...

Page 13: ...scheme of releted Main Link select 0 LOCKN1 1 LOCKN0 LOCKN1 2 Reserved 3 1 b0 Forced LOCKN HTPDN Low LOCKN1 LOCKN signal of V by One R HS Lane1 RX1P RX1N HTPDN of the same lane as above set LOCKN lane is used 2 d0 1 0 R_LOCKN_LN0_SEL 2 RW Sub Link Lane0 LOCKN HTPDN scheme of releted Main Link select 0 LOCKN0 1 LOCKN0 LOCKN1 2 Reserved 3 1 b0 Forced LOCKN HTPDN Low LOCKN0 LOCKN signal of V by One R...

Page 14: ... As an additional method 2 wire slave Device ID setting can be changed from default value by register setting Table 8 2 wire serial I F Device ID select by register setting AIN1 37 I1 AIN0 36 I1 Device Address Setting for 2 w ire Serial Interface AIN1 AIN0 00 ID 7 h0B AIN1 AIN0 01 ID 7 h34 AIN1 AIN0 10 ID 7 h77 AIN1 AIN0 11 ID 7 h65 Addr h bit Register Name width R W Description Default 0x0030 7 0...

Page 15: ... THCV242 Sub Link Block Register 2 wire Slave Host MPU SCL AIN 1 0 User Select SDA S Register address MSB Device ID W A S P A A W Start condition Stop condition ACK NACK Write command indicator Access from 2 wire serial interface Master Access from 2 wire serial interface Slave Register address LSB A A Write data 1 A A P S Register address MSB Device ID W A S P A A W R Start condition Stop conditi...

Page 16: ...o monitor status Table 9 2 wire WDT setting Addr h bit Register Name width R W Description Default 0x003B 7 5 reserved 3 4 R_2WIRE_WD_EN 1 RW 2WIRE WDT Enable 0 Disable 1 Enable 1 b1 3 1 reserved 3 0 R_2WIRE_WD_OFFSET 1 RW 2WIRE_WDT_OffsetTime 1 11 d2047 0 11 d1023 1 d1 0x003C 7 0 R_2WIRE_WD_TIM 8 RW 2WIRE WDT_time 64 R_2WIRE_WD_TIM 7 0 1 2WIRE_WDT_OffsetTime tOSC 8 d255 ...

Page 17: ...th R W Description Default 0x0004 7 3 reserved 5 2 0 R_SLINK_MODE 3 RW Sub Link basic protocol setting as Sub Link Master 1 2 wire Set Trigger Normal mode1 3 2 wire Pass Through mode1 0 2 4 5 6 7 Reserved 3 d1 0x0010 7 4 R_SLINK_EN 4 RW Sub Link Enable 7 Reserved 6 Reserved 5 0 Lane1 Disable 1 Lane1 Enable 4 0 Lane0 Disable 1 Lane0 Enable 4 d0 3 0 R_SLINK_POL_EN 4 RW Sub Link Polling Enable 3 Rese...

Page 18: ...gister control and monitoring on 2 wire Set Trigger mode1 Figure 7 Host MPU to remote 2 wire slave devices via THCV242 access configuration Sub Link Block 2 wire Slave Sub Link Master THCV242 as Sub Link Master Sub Link Slave Device Sub Link Block Sub Link Slave 2 wire Master Sub Link line AIN 1 0 User Select Interrupt signal MSSEL 1 Host MPU SCL SDA INT Register Register Triggered access by Sub L...

Page 19: ...When R_2WIRE_CLKSEN 0 Sub Link Master device informs HOST MPU that Sub Link Slave register access or remote side 2 wire serial register access has completed by interruption detectable on INT pin without clock stretching Figure 8 Sub Link Master 2 wire slave clock stretching operation 2 wire Write A SD1 SCL SD0 SDA Access start to Sub Link Slave s register or Remote side 2 wire serial Slave s regis...

Page 20: ..._2WIRE_DATA15 8 RW 2 wire serial I F remote write read data 15 8 d0 0x00E0 7 1 R_2WIRE_DEVADR 7 RW 2 wire serial I F remote access target device address if target self addr access to Sub Link Slave inside register else access to remote side 2 wire serial Slave devices externally connected to Sub Link slave 7 h00 0 R_2WIRE_WR 1 RW 2 wire serial I F remote access write or read select 0 Write 1 Read ...

Page 21: ...mand Divided scheme On address processing protocol Assigned address rename THCV242 2 wire slave respond only to 2 wire device address defined in R_2WIREPT1_PASS_ADRxy1 x Lane0 or Lane1 y 0 1 2 3 for remote Pass Through operation Otherwise 2 wire commands are ignored except THCV242 itself address The device address can be renamed before remote send The counterpart Sub Link Slave internal register a...

Page 22: ...to send for Lane0 1 being active only at R_2WIREPT_MODE 0 0 8 d0 0x0044 7 0 R_2WIREPT1_PASS_ADR020 8 RW 2WIRE Pass Through received before rename address for Lane0 2 being active only at R_2WIREPT_MODE 0 0 8 d0 0x0045 7 0 R_2WIREPT1_PASS_ADR021 8 RW 2WIRE Pass Through after renamed address to send for Lane0 2 being active only at R_2WIREPT_MODE 0 0 8 d0 0x0046 7 0 R_2WIREPT1_PASS_ADR030 8 RW 2WIRE...

Page 23: ...ugh after renamed address to send for Lane1 3 being active only at R_2WIREPT_MODE 0 0 8 d0 0x0068 7 0 R_2WIREPT2_NOPASS_ADR10 8 RW 2WIRE Pass Through ignore address otherwise All Through fror Lane1 0 being active only at R_2WIREPT_MODE 0 1 8 d0 0x0069 7 0 R_2WIREPT2_NOPASS_ADR11 8 RW 2WIRE Pass Through ignore address otherwise All Through fror Lane1 1 being active only at R_2WIREPT_MODE 0 1 8 d0 0...

Page 24: ...g Timer Clear by GPI mode Enable 2 Polling Timer Mask by GPI mode Enable 3 Disable 2 d0 3 reserved 1 2 0 R_GPI_TRG_SEL 3 RW Polling Timer Clear Mask GPI select 0 GPI0 1 GPI1 2 GPI2 3 GPI3 4 GPI4 5 GPI5 6 GPI6 7 GPI7 Only 0and1 are available at 2 wire mode1 R_SLINK_MODE 1 0 2 d1 3 d0 Trigger GPI Sub Link Master Polling transaction to all Sub Link lanes Cleared new Polling Interval Polling Timer Cle...

Page 25: ...Reserved 0x10 02 7 4 R_GPIO5_MODE 4 R W 4 h0 GPIO5 I O Mode 0 Disable 1 Programable GPO Output Low 2 Programable GPO Output High 3 Through GPI Mode 4 Through GPO Mode 5 Second 2WIRE Mode SCL 6 Second 2WIRE Mode SDA 7 F Reserved 0x10 02 3 0 R_GPIO4_MODE 4 R W 4 h0 GPIO4 I O Mode 0 Disable 1 Programable GPO Output Low 2 Programable GPO Output High 3 Through GPI Mode 4 Through GPO Mode 5 Second 2WIRE...

Page 26: ...0 04 7 4 R_GPIO1_MODE 4 R W 4 h0 GPIO1 I O Mode 0 Disable 1 Programable GPO Output Low 2 Programable GPO Output High 3 Through GPI Mode 4 Through GPO Mode 5 Second 2WIREMode SCL 6 Second 2WIREMode SDA 7 F Reserved 0x10 04 3 0 R_GPIO0_MODE 4 R W 4 h0 GPIO0 I O Mode 0 Disable 1 Programable GPO Output Low 2 Programable GPO Output High 3 Through GPI Mode 4 Through GPO Mode 5 Second 2WIREMode SCL 6 Sec...

Page 27: ...g with THCV241 as Sub Link Slave communication THCV242 as Sub Link Master GPIO0 1 are dedicated to GPI to Sub Link Lane0 GPIO2 3 are dedicated to GPI to Sub Link Lane1 GPIO2 3 are also dedicated to GPO from selected Sub Link Lane Figure 12 Through GPIO via Sub Link transaction assignment with THCV241 Remote UART bridge is supported with Sub Link Through GPIO input output Remote UART Tx and Rx brid...

Page 28: ... 2 00_E Copyright 2019 THine Electronics Inc THine Electronics Inc 28 53 Security E GPIO as secondary 2 wire port GPIO port can be secondary 2 wire port which can accommodate dual 2 wire access from two processors ...

Page 29: ...RefDiv symbol discription min typ max unit F IN PLL input pixel clock frequency 10 133 3 MHz RefDiv Reference Divider value 1 7 FBDiv FeedBack Divider value 20 130 OutDiv1 1st Output Divider value OutDiv1 must be OutDiv2 1 7 OutDiv2 2nd Output Divider value OutDiv1 must be OutDiv2 1 7 F PFD PFD frequency 10 MHz F VCO VCO frequency 500 1300 MHz F OUT PLL output pixel clock frequency 80 1200 MHz PCL...

Page 30: ... 24 32 Main Link input lane 4 8 MIPI output lane F MIPI output F Main Link input frequency ratio Format index condition Main Link input MIPI output Distribution F MLINK in F VCO F MIPI out PLL 47 40 PLL 39 32 PLL 31 24 PLL 23 16 PLL 15 8 PLL 7 0 1 off 18 5625 1188 594 0x40 0x01 0x21 0x00 0x00 0x00 3 720p30fps YUV422 750Mbps 1lane MPRF 600Mbps x1lane off 18 75 1200 600 0x40 0x01 0x21 0x00 0x00 0x00...

Page 31: ...7 5 3 b000 4 0 R W 5 b0000_0 R_MODE_NO Main Link input data stream handling mode number 5 d0 1 2 3 8 10 11 are available Others reserved Register Name Description Reserved Handling Input R_MODE_NO Camera Main Link_0 Main Link_1 MIPI_0 MIPI_1 5 d0 1 Disable 1 Cam A Cam A 5 d1 1 Enable 2 Cam A Cam A Cam A 5 d2 1 Disable 1 Cam B Cam B 5 d3 1 Enable 2 Cam B Cam B Cam B 5 d8 1 2port Disable 1 Cam A Cam...

Page 32: ...n Link Lane0 to MIPI Word Count MSB 8bit manual setting Only active when R_VX1_PH_EN 0 R_VX1_WC_LOW0 Main Link Lane0 to MIPI Word Count LSB 8bit manual setting Only active when R_VX1_PH_EN 0 Reserved R_VX1_VSYNC_POL0 Main Link Lane0 VSYNC intake polarity 1 b0 Low active VSYNC Low pulse 1 b1 High active VSYNC High pulse Reserved R_VX1_VVALID_MODE0 Main Link Lane0 to MIPI VVALID generation mode 1 b0...

Page 33: ...be set 1 0 ReservedL Must be set 0 R_TX_LANE_SEL0 MIPI Tx Lane assignment select SWAP 7 6 Lane3 5 4 Lane2 3 2 Lane1 1 0 Lane0 2 b00 1st Byte output 2 b01 2nd Byte output 2 b10 3rd Byte output 2 b11 4th Byte output On 2port output configuration 3rd and 4th Byte are 2nd PORT1 On 2port 1lane output configuration 1st and 3rd Byte are used Reserved R_TX_LANE_SEL1 MIPI 2port output 2nd PORT1 select Sele...

Page 34: ...K_PRE1 CLK lane PRE period setting PORT1 R_TX_CLK_TRAIL1 CLK lane TRAIL period setting PORT1 R_TX_CLK_ZERO1 CLK lane ZERO period setting PORT1 R_TX_CLK_PREPARE1 CLK lane PrePare period setting PORT1 R_TX_THS_TRAIL0 Data lane TRAIL period setting PORT0 R_TX_THS_ZERO0 Data lane ZERO period setting PORT0 R_TX_THS_PREPARE0 Data lane Prepare period setting PORT0 R_TX_TLPX0 Data lane TLPX period setting...

Page 35: ...nd port1 clock THCV242 R_TX_LANE_SEL1 lane3 lane2 lane1 lane0 port1 select port enable clk enable config lane3 lane2 lane1 lane0 lane3 lane1 lane0 lane2 7 6 5 4 3 2 1 0 1 0 6 5 4 3 2 0 3 2 1 0 MTX3P N MTX1P N MTXCLK0P N MTX0P N MTX2P N MTXCLK1P N 01 11 00 10 00 11 11 101 0 1 0 1 port0 2nd Byte port0 1st Byte port0 clock port1 1st Byte port1 2nd Byte port1 clock 01 10 00 11 10 11 11 101 0 1 0 1 por...

Page 36: ... clock and video pixel clock from Main Link input At the beginning of internal VSYNC generation operation oscillator clock is used to supply VSYNC After Main Link video source is received stable internal VSYNC generation source is switched to video pixel clock from selected Main Link input When Main Link video pixel clock input is lost internal VSYNC generator again uses internal oscillator clock ...

Page 37: ...pulse width line number by oscillator setting Line Number R_VSOSC_WIDTH 1 e g 0x0 for 1line 8 d4 0x0026 7 4 reserved 4 3 0 R_VSOSC_TIM_UP 4 RW Internal VSYNC pulse interval line number by oscillator setting 4 d0 0x0027 7 0 R_VSOSC_TIM_DN 8 RW Internal VSYNC pulse interval line number by oscillator 256 R_VSOSC_TIM_UP 3 0 R_VSOSC_TIM_DN 7 0 1 tOSC Interval line is 2 when R_VSOSC_TIM_UP 0 and R_VSOSC...

Page 38: ...OCKN_ALL OR operated of all operating lanes 0x03 Vx1_HTPDN_ALL OR operated of all operating lanes 0x04 Vx1_FBETOUT_LATCH_ALL OR operated of all operating lanes 0x05 Vx1_FBETOUT_REAL_ALL OR operated of all operating lanes 0x06 Vx1_PERR_ALL OR operated of all operating lanes protocol error 0x07 MLINK_CRCERR_ALL OR operated of all operating lanes 0x08 Vx1_CLOCKSTP_ALL clock stop detector of all lanes...

Page 39: ...rved 0x24 MLINK_CRCERR0 lane0 0x25 MLINK_CRCERR1 lane1 0x26 Reserved 0x27 Reserved 0x28 MLINK_VSYNC0 lane0 0x29 MLINK_VSYNC1 lane1 0x2A Reserved 0x2B Reserved 0x2C MLINK_HSYNC0 lane0 0x2D MLINK_HSYNC1 lane1 0x2E Reserved 0x2F Reserved 0x30 MLINK_DE0 lane0 0x31 MLINK_DE1 lane1 0x32 Reserved 0x33 Reserved 0x34 MLINK_CLK0 lane0 0x35 MLINK_CLK1 lane1 0x36 Reserved 0x37 Reserved 0x38 MIPI_BYTECLK 0x39 ...

Page 40: ... lane1 Frame End 0x46 Reserved 0x47 Reserved 0x48 MLINK_VDSK_NG0 lane0 Vsync synchronization NG flag 0x49 MLINK_VDSK_NG1 lane1 Vsync synchronization NG flag 0x4A Reserved 0x4B Reserved 0x4C TOP_CKSUM_ERR register checksum error 0x4D Reserved 0x4E Reserved 0x4F Reserved 0x50 Reserved 0x51 Reserved 0x52 Reserved 0x53 Reserved 0x54 SLINK_PERR0 lane0 protocol error 0x55 SLINK_PERR1 lane1 protocol erro...

Page 41: ... R_SLINK_FBETERR_NUM_UP 7 0 R_SLINK_FBETERR_NUM_DN 7 0 bit Register Name width R W init Description 0x17 4F 7 4 R_MLINK_CRC_ERRCLR 4 W Main Link CRC Error Counter Clear 1 Clear 3 0 R_MLINK_BET_ERRCLR 4 W Main Link BET Error Counter Clear 1 Clear 0x17 50 7 0 MLINK0_CRC_ERRNUM 15 8 8 R Main Link Lane0 CRC Error Number Upper Byte 0x17 51 7 0 MLINK0_CRC_ERRNUM 7 0 8 R Main Link Lane0 CRC Error Number ...

Page 42: ...am Handler Distribution error 4 Data Stream Handler error 3 Reserved 2 Reserved 1 MAINLINKRX CRC error for Lane1 0 MAINLINKRX CRC error for Lane0 1 MIPI CSI 2 ULPS END signal PORT1 0 MIPI CSI 2 ULPS END signal PORT0 6 MIPI CSI 2 general error 5 MIPI CSI 2 EOT error for CLK Lane1 4 MIPI CSI 2 EOT error for CLK Lane0 3 MIPI CSI 2 SOT error for Data Lane3 2 MIPI CSI 2 SOT error for Data Lane2 1 MIPI ...

Page 43: ...tion Register Auto Checksum diagnosis Register values checksum is continuously calculated as R_CKSUM_RVAL Table 33 Register Auto Checksum diagnosis control and monitoring bit Register Name width R W init Description 0x10 06 7 4 R_INT1_MODE 4 R W 4 h0 INT1 I O Mode 0 Disable 1 OpenDrain Output Mode 2 Push Pull Output Mode 3 F Reserved 0x10 06 3 0 R_INT0_MODE 4 R W 4 h0 INT0 I O Mode 0 Disable 1 Ope...

Page 44: ...mum 1frame which depends on used video format Operating Condition min Operating Condition min t1 t2 VIH VIL Polling Polling t3 t12 Hi Z t6 Hi Z MIPI LP11 HS mode VDDH 3 3V 1 8V domain VDD12 1 2V domain PDN THCV242 PowerON 2 wire access prohibited t11 2 wire remote access THCV242 settings Sub Link slave IC settings 2 wire SCL SDA MIPI Tx soft reset MIPI Tx TXN P V by One HS Rx Soft reset V by One H...

Page 45: ...k Tx LOCKN Low to Data pattern output delay THCV242 MTXmP MTXmN m 0 1 2 3 t6 Normal Operation Normal Operation THCV242 LOCK Sequence MIPI LP11 THCV242 LOCKN THCV242 Sub Link Master polling worst case LOCKN L LOCKN H One poling Polling Interval THCV242 RXnP RXnN n 0 1 CDR Training t12 ALN Training Normal Operation LOCKN H LOCKN L Polling Interval One poling Main Link Tx LOCKN H to Training pattern ...

Page 46: ...MOS Output Voltage 0 3 VDDIO1 0 3 1 V LVCMOS Bi directional buffer Input Voltage 0 3 VDDIO1 0 3 1 V LVCMOS Bi directional buffer Output Voltage 0 3 VDDIO1 0 3 1 V LVCMOS Input Voltage VDDIO2 domain 0 3 VDDIO2 0 3 1 V CML Receiver Voltage 0 3 VDDRX 0 3 2 V MIPI Transmitter Voltage 0 3 VDDTX 0 3 2 V CML Bi directional buffer Input Voltage 0 3 VDDIO2 0 3 1 V CML Bi directional buffer Output Voltage 0...

Page 47: ...0 148 mA Iccw12_34 102 165 mA Iccw12_35 102 164 mA Iccw12_36 120 186 mA Iccw12_37 121 186 mA Iccw12_38 151 219 mA Iccw12_39 153 226 mA Iccw12_402 184 258 mA Iccw12_412 188 266 mA 2 97Gbps x1lane x2port 1188Mbps x2lane x2port 1080p60fps YUV422 2 2 1 485Gbps x1lane x2port 594Mbps x2lane x2port 1080p30fps YUV422 720p120fps RAW 2 2275Gbps x1lane x2port 891Mbps x2lane x2port 1080p60fps RAW 742 5Mbps x1...

Page 48: ...x 2 5V 0 0 30 VDDIO V VDDIOx 1 8V 0 0 35 VDDIO V VDDIOx 3 3V VDDIO 0 6 VDDIO V VDDIOx 2 5V VDDIO 0 5 VDDIO V VDDIOx 1 8V VDDIO 0 45 VDDIO V VOL LVCMOS Low Level Output Voltage 0 0 45 V VIH VIL LVCMOS High Level Input Voltage LVCMOS Low Level Input Voltage VOH LVCMOS High Level Output Voltage Symbol Parameter Condition min typ max Unit VRTH CML Differential Input High Threshold 50 mV VRTL CML Diffe...

Page 49: ...it ITIL Input Leak Current Low PDN 0 10 10 uA ITIH Input Leak Current High PDN 0 10 10 uA VTCMTX HS mode statics Common mode Voltage ZID 80 125ohm 160 200 240 mV VTOD HS mode Differential Voltage ZID 100ohm 150 200 260 mV VTOHHS HS mode High Level Output Voltage ZID 100ohm 350 mV VTOHLP LP mode High Level Output Voltage 1 1 1 3 V VTOLLP LP mode Low Level Output Voltage 0 05 0 05 V ZTOLP LP mode Ou...

Page 50: ... TCMP N 0V 10 10 uA VBOD CML Bi Directional Buffer Differential Output Voltage R_BDCZ_TERM_ 1 0 2 b10 R_BDCZ_DRIVE_ 1 0 2 b10 Diff 100ohm terminated 200 300 400 mV VBOC CML Bi Directional Buffer Common Output Voltage R_BDCZ_TERM_ 1 0 2 b00 R_BDCZ_DRIVE_ 1 0 2 b00 VDDB 300 mV IBOZ CML Bi Directional Buffer TRI STATECurrent PDN1 0 10 10 uA R_BDCZ_TERM_TX RX 1 0 2 b10 50 ohm R_BDCZ_TERM_TX RX 1 0 2 b...

Page 51: ...wire serial Slave AC Specifications Table 49 2 wire serial Slave AC Specifications Sub Link Master Symbol Parameter Condition Min Typ Max Unit tDL Data Latency MainLink 1Gbps Data stream handling mode1 Typ 98 16000 Typ 98 ns Symbol Parameter Condition min typ max Unit 250 2500 ps 0 4 4 Gbps Unit Interval tRBIT Symbol Parameter Conditions min typ max Unit 0 833 12 5 ns 80 1200 Mbps tTBIT Tx Unit In...

Page 52: ... THine Electronics Inc THine Electronics Inc 52 53 Security E 12 Package LASER MARK FOR PIN1 9 0 0 65 0 9 MAX TOP VIEW 9 0 BOTTOM VIEW 6 00 6 00 1 10 0 45 1 10 0 5 0 25 0 4 1 16 17 32 33 48 49 64 PIN1 ID 0 20 R 0 09 R SIDE VIEW Unit mm ...

Page 53: ...product is specified as a product conforming to the demands and specifications of IATF16949 the Specified Product in this data sheet THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications 5 3 THine accepts liability for demands and specifications of the Specified Product only to the extent that t...

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