Programming Model
TVP4020
Programmers Reference Manual
22
Drivers may choose to use direct access to memory for algorithms which
are not supported by P
ERMEDIA
or for better performance in some
specific cases. This may be so, for example, when multiple pixels can be
written simultaneously and there is minimal host software overhead.
A driver making use of the bypass mechanism should synchronize
memory accesses made through the FIFO with those made directly
through the memory map. If data is written to the FIFO and then an
access is made to the memory, it is possible that the memory access will
occur before the commands in the FIFO have been fully processed. This
lack of temporal ordering is generally undesirable.
There are two windows through which the memory can be accessed.
Each window can have its own data formatting control that allows for
different forms of byte swapping and data packing. If the framebuffer is
set to use the 5:5:5:1Front and 5:5:5:1Back color modes, two pixels are
packed into each 32 bit word, but each pixel belongs to a different buffer.
Adjacent pixels in the same buffer are separated by 16 bits. As some
software has difficulty with pixels that are not packed together, the
memory windows can be configured to remap the data so that only the
front or back buffer is visible, and it appears packed.
3.6
DMA Controller
A DMA controller is provided to allow transfer of data from the PCI bus to
P
ERMEDIA
memory. This controller is independent of the DMA controller
which feeds the Graphics Processor FIFO, and has support for
rectangular data structures and data formatting.
3.7
Register Read back
Under some operating environments, multiple tasks will want access to
the P
ERMEDIA
chip. Sometimes a server task or driver will want to
arbitrate access to P
ERMEDIA
on behalf of multiple applications. In these
circumstances, the state of the P
ERMEDIA
chip may need to be saved and
restored on each context switch. To facilitate this, the P
ERMEDIA
registers
can be read back. For details of which registers are readable, see
Appendix D Register Tables. Internal and command registers cannot be
read back.
To perform a context switch the host must first synchronize with
P
ERMEDIA
. This means sending a Sync command and waiting for the
sync output data to appear in the output FIFO. After this the registers
can be read back.
Summary of Contents for TVP4020 PERMEDIA 2
Page 1: ...Texas Instruments TVP4020 PERMEDIA 2 Programmer s Reference Manual Issue 4 ...
Page 284: ...TVP4020 Programmers Reference Manual A Gouraud Shaded Triangle 275 ...
Page 292: ...TVP4020 Programmers Reference Manual Register Tables 283 ...
Page 314: ...TVP4020 Programmers Reference Manual Index 305 ...
Page 315: ...Index TVP4020 Programmers Reference Manual 306 Index ...
Page 323: ...Index TVP4020 Programmers Reference Manual 314 ...