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Programming Model
TVP4020
Programmers Reference Manual
20
Note, that when writing to the raw FIFO address the FIFO full condition
must still be checked by reading the InFIFOSpace register. However,
writing tag descriptions does not cause any entries to be entered into the
FIFO – such a write simply establishes a set of tags to be paired with the
subsequent data. Thus, free space need be ensured only for actual data
items that are written (not the tag values). For example, in the simplest
case where each tag is followed by a single data item, assuming that the
FIFO is empty, then 32 writes are possible before checking again for
free space.
See the
TVP4020 Hardware Reference Manual for more details of the
Graphics Processor FIFO Interface address range.
3.3
Interrupts
All interrupts can be individually enabled and disabled. Refer to the
TVP4020 Hardware Reference Manual for more details.
3.4
Synchronization
There are two main cases where the host must synchronize with
P
ERMEDIA
:
•
before reading back from P
ERMEDIA
registers
•
before directly accessing the memory via the bypass mechanism
Also the host must synchronize with P
ERMEDIA for
framebuffer
management tasks such as double buffering, though this may be better
handled using the SuspendUntilFrameBlank command. Synchronizing
with P
ERMEDIA
implies waiting for any pending DMA to complete and
waiting for the chip to complete any processing currently being
performed. The following pseudo-code shows the general scheme:
Summary of Contents for TVP4020 PERMEDIA 2
Page 1: ...Texas Instruments TVP4020 PERMEDIA 2 Programmer s Reference Manual Issue 4 ...
Page 284: ...TVP4020 Programmers Reference Manual A Gouraud Shaded Triangle 275 ...
Page 292: ...TVP4020 Programmers Reference Manual Register Tables 283 ...
Page 314: ...TVP4020 Programmers Reference Manual Index 305 ...
Page 315: ...Index TVP4020 Programmers Reference Manual 306 Index ...
Page 323: ...Index TVP4020 Programmers Reference Manual 314 ...