TRF7970A
MCU
(MSP430 or ARM)
Matching
V
DD_X
V
DD_I/O
TX_OUT
RX_IN 1
RX_IN2
V
SS
V
IN
Parallel
or SPI
Supply: 2.7 V to 5.5 V
V
DD
V
DD
Crystal
13.56 MHz
XIN
13
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
Product Folder Links:
Detailed Description
Copyright © 2011–2017, Texas Instruments Incorporated
6
Detailed Description
6.1
Overview
6.1.1
RFID and NFC Operation – Reader and Writer
The TRF7970A is a high-performance 13.56-MHz HF RFID and NFC transceiver IC composed of an
integrated analog front end (AFE) and a built-in data framing engine for ISO/IEC 15693, ISO/IEC 14443 A
and B, and FeliCa. This includes data rates up to 848 kbps for ISO/IEC 14443 with all framing and
synchronization tasks on board (in default mode). The TRF7970A also supports NFC tag type 1, 2, 3, 4,
and 5 operations. This architecture lets the customer build a complete cost-effective yet high-performance
multiprotocol 13.56-MHz RFID and NFC system together with a low-cost microcontroller.
Other standards and even custom protocols can be implemented by using either of the direct modes that
the device offers. These direct modes (0 and 1) allow the user to fully control the analog front end (AFE)
and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the
associated (extracted) clock signal.
The receiver system has a dual input receiver architecture. The receivers also include various automatic
and manual gain control options. The received input bandwidth can be selected to cover a broad range of
input subcarrier signal options.
The received signal strength from transponders, ambient sources, or internal levels is available through
the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the
integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data
clock as outputs.
The TRF7970A also includes a receiver framing engine. This receiver framing engine performs the CRC
or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO/IEC 14443 A
and B, ISO/IEC 15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU)
through a 127-byte FIFO register.
Figure 6-1. Application Block Diagram
A parallel or serial interface (SPI) can be used for the communication between the MCU and the
TRF7970A reader. When the built-in hardware encoders and decoders are used, transmit and receive
functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and
decoders can be bypassed so that the MCU can process the data in real time. The TRF7970A supports
data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has
selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-
Ω
load
when using a 5-V supply.
