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SLOS743L – AUGUST 2011 – REVISED MARCH 2017

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Detailed Description

Copyright © 2011–2017, Texas Instruments Incorporated

Step 4: Entering Direct Mode 0

The following registers must be programmed to enter direct mode 0:

1. Set bit B6 of the Modulator and SYS_CLK Control register (0x09) to 1.

2. Set bit B6 of the ISO Control (Register 01) to 0 for direct mode 0 (default its 0)

3. Set bit B6 of the Chip Status Control register (0x00) to 1 to enter direct mode

4. Send extra eight clock cycles (see

, this step is TRF7970A specific)

NOTE

•

It is important that the last write is not terminated with a stop condition. For SPI, this
means that Slave Select (I/O_4) stays low.

•

Sending a Stop condition terminates the direct mode and clears bit B6 in the Chip Status
Control register (0x00).

NOTE

Access to Registers, FIFO, and IRQ is not available during direct mode 0.

The reader enters the direct mode 0 when bit 6 of the Chip Status Control register (0x00) is set to a 1 and
stays in direct mode 0 until a stop condition is sent from the microcontroller.

NOTE

The write command should not be terminated with a stop condition (for example, in SPI
mode this is done by bringing the Slave Select line high after the register write), because the
stop condition terminates the direct mode and clears bit 6 of the Chip Status Control register
(0x00), making it a 0.

Figure 6-28. Entering Direct Mode 0

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Summary of Contents for TRF7970A BoosterPack

Page 1: ...Reader System or Ambient In Band Noise Detection Programmable Power Modes for Ultra Low Power System Design Power Down 1 µA Parallel or SPI Interface With 127 Byte FIFO Temperature Range 40 C to 110 C 32 Pin QFN Package 5 mm 5 mm 1 2 Applications Mobile Devices Tablets Handsets Secure Pairing Bluetooth Wi Fi Other Paired Wireless Networks Public Transport or Event Ticketing Passport or Payment POS...

Page 2: ...ders can be bypassed so the MCU can process the data in real time The TRF7970A device supports a wide supply voltage range of 2 7 V to 5 5 V and data communication levels from 1 8 V to 5 5 V for the MCU I O interface The transmitter has selectable output power levels of 100 mW 20 dBm or 200 mW 23 dBm equivalent into a 50 Ω load when using a 5 V supply and supports OOK and ASK modulation with selec...

Page 3: ...T VDD_PA VSS_PA Digital Control State Machine Crystal or Oscillator Timing System EN EN2 ASK OOK MOD OSC_IN OSC_OUT Voltage Supply Regulator Systems Supply Regulators and Reference Voltages VSS_A VSS_RF VDD_RF VDD_X VSS_D VSS VIN VDD_A BAND_GAP RF Level Detector Phase and Amplitude Detector Copyright 2017 Texas Instruments Incorporated 3 TRF7970A www ti com SLOS743L AUGUST 2011 REVISED MARCH 2017 ...

Page 4: ...16 6 4 Receiver Analog Section 22 6 5 Receiver Digital Section 23 6 6 Oscillator Section 28 6 7 Transmitter Analog Section 29 6 8 Transmitter Digital Section 30 6 9 Transmitter External Power Amplifier and Subcarrier Detector 31 6 10 TRF7970A IC Communication Interface 31 6 11 TRF7970A Initialization 49 6 12 Special Direct Mode for Improved MIFARE Compatibility 50 6 13 NFC Modes 50 6 14 Direct Com...

Page 5: ...ged coded as ISO14443 to SENSB_REQ in the bulleted list item that starts If the first command is a SENSB_REQ in Section 6 1 3 NFC Device Operation Target 15 Changed FeliCa to peer to peer in Section 6 1 3 1 Active Target and Section 6 1 3 2 Passive Target 15 Updated the paragraph that starts The transmission of a response must occur after RF collision avoidance in Section 6 1 3 1 Active Target 15 ...

Page 6: ...e 0x15 Close Slot Sequence from Table 6 19 Address and Command Word Bit Distribution 52 Added the sentence that starts This command should be sent after a Software Initialization command in Section 6 14 1 1 Idle 0x00 53 Changed the description in Section 6 14 1 3 Initial RF Collision Avoidance 0x04 54 Changed the description in Section 6 14 1 4 Response RF Collision Avoidance 0x05 54 Changed the d...

Page 7: ...ucts For information about other devices in this family of products or related products see the following links Products for TI Wireless Connectivity Connect more with the industry s broadest wireless connectivity portfolio Products for NFC RFID TI provides one of the industry s most differentiated NFC and RFID product portfolios and is your solution to meet a broad range of NFC connectivity and R...

Page 8: ...ribes the signals Table 4 1 Terminal Functions TERMINAL TYPE 1 DESCRIPTION NAME NO VDD_A 1 OUT Internal regulated supply 2 7 V to 3 4 V for analog circuitry VIN 2 SUP External supply input to chip 2 7 V to 5 5 V VDD_RF 3 OUT Internal regulated supply 2 7 V to 5 V normally connected to VDD_PA pin 4 VDD_PA 4 INP Supply for PA normally connected externally to VDD_RF pin 3 TX_OUT 5 OUT RF output selec...

Page 9: ... direct mode 1 and special direct mode I O_6 23 BID I O pin for parallel communication MISO for serial communication SPI Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0 I O_7 24 BID I O pin for parallel communication MOSI for serial communication SPI EN2 25 INP Selection of power down mode If EN2 is connected to VIN then VDD_X is active during power down mode 2 for ex...

Page 10: ... Maximum current VIN 150 mA TJ Maximum operating virtual junction temperature Any condition 140 C Continuous operation long term reliability 3 125 C TSTG Storage temperature 55 150 C 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process Pins listed as 2000 V may actually have higher performance 2 JEDEC document JEP157 states that 250 V CDM allo...

Page 11: ...upply current in stand by mode Oscillator running supply voltage regulators in low consumption mode EN 1 EN2 x 1 9 3 5 mA ION1 Supply current without antenna driver current Oscillator regulators RX and AGC active TX is off 10 5 14 mA ION2 Supply current TX half power Oscillator regulators RX and AGC and TX active POUT 100 mW 70 78 mA ION3 Supply current TX full power Oscillator regulators RX and A...

Page 12: ...hen external capacitive load is less than 30 pF MISO driver has a typical output resistance of 400 Ω 12 ns time constant when 30 pF load used 5 6 Switching Characteristics TYP operating conditions are TA 25 C VIN 5 V full power mode unless otherwise noted MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMET...

Page 13: ...nal The receiver system has a dual input receiver architecture The receivers also include various automatic and manual gain control options The received input bandwidth can be selected to cover a broad range of input subcarrier signal options The received signal strength from transponders ambient sources or internal levels is available through the RSSI register The receiver output is selectable am...

Page 14: ...n Target The activation of NFC target is done when a sufficient RF field level is detected on the antenna The level needed for wake up is selectable and is stored in a nonvolatile register When the activation occurs the system performs automatic power up and waits for the first command to be received Based on this command the system knows if it should operate as passive or active target and at wha...

Page 15: ...d is a SENSB_REQ request and the card emulation bit is set in the ISO Control register the system enters ISO IEC 14443 B emulation mode The anticollision must be handled by the MCU and the chip provides all physical level coding decoding and framing for this protocol 6 1 3 1 Active Target If the first command received by the RF interface defines the system as an active target then the receiver sel...

Page 16: ...ich relieves the MCU of any real time tasks however this method can present interoperability challenges with other NFC devices due to timing requirements To ensure best interoperability TI recommends allowing the MCU to manage the anticollision process instead The unique ID required for anticollision is provided by the MCU after wakeup of the system 6 2 System Block Diagram Figure 6 2 shows a bloc...

Page 17: ...oltage is fixed at 3 4 V External bypass capacitors for supply noise filtering must be used per reference schematics When configured for 3 V manual operation the VDD_A output can be set from 2 7 V to 3 4 V in 100 mV steps see Table 6 2 NOTE The configuration of VDD_A and VDD_X regulators are not independent from each other The VDD_X output current should not exceed 20 mA Digital Supply Regulator V...

Page 18: ... input voltage ranges from 1 8 V to VIN not exceeding 5 5 V Pin 16 is used to supply the I O interface pins I O_0 to I O_7 IRQ SYS_CLK and DATA_CLK pins of the reader In typical applications VDD_I O is directly connected to VDD_X while VDD_X also supplies the MCU This ensures that the I O signal levels of the MCU match the logic levels of the TRF7970A Negative Supply Connections VSS VSS_TX VSS_RX ...

Page 19: ...ator setting 400 mV difference Manual Mode 0B 0 x x x x 1 1 1 VDD_RF 5 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 1 1 0 VDD_RF 4 9 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 1 0 1 VDD_RF 4 8 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 1 0 0 VDD_RF 4 7 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 0 1 1 VDD_RF 4 6 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 0 1 0 VDD_RF 4 5 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 0 0 1 VDD_...

Page 20: ...DC X 1 03 07 OFF ON ON X ON 10 5 Mode 3 half power at 5 VDC X 1 31 07 ON ON ON X ON 70 20 Mode 4 full power at 5 VDC X 1 21 07 ON ON ON X ON 130 23 Table 6 3 and Table 6 4 show the configuration for the different power modes when using a 3 3 V or 5 V system supply respectively The main reader enable signal is pin EN When EN is set high all of the reader regulators are enabled the 13 56 MHz oscilla...

Page 21: ...and states are listed in Table 6 3 When EN is set high or on rising edge of EN2 and then confirmed by EN 1 the supply regulators are activated and the 13 56 MHz oscillator is started When the supplies are settled and the oscillator frequency is stable the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13 56 MHz frequency derived from the crystal oscillator At this point t...

Page 22: ...e default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver To determine the signal quality the response from the tag is detected by the main pin RX_IN1 and auxiliary pin RX_IN2 RSSI Both values measured and stored in the RSSI Levels and Oscillator Status register address 0x0F The MCU can read the RSSI values from the TRF7970A RSSI register and mak...

Page 23: ...nterference The framing logic section formats the serial bit stream data from the protocol bit decoder stage into data bytes During the formatting process special signals such as the start of frame SOF end of frame EOF start of communication and end of communication are automatically removed The parity bits and CRC bytes are also checked and removed The end result is clean or raw data that is sent...

Page 24: ...ot active held in reset state This prevents false detections resulting from transients following the transmit operation The value of the RX Wait Time register 0x08 defines the time in increments of 9 44 µs This register is preset at every write to the ISO Control register 0x01 according to the minimum tag response time defined by each standard The RX no response timer is controlled by the RX No Re...

Page 25: ... decoder selected by ISO bits B5 rfid RFID mode 0 RFID reader mode 1 NFC or card emulator mode B4 iso_4 RFID protocol NFC target RFID Mode selection NFC 0 NFC target 1 NFC initiator B3 iso_3 RFID protocol NFC mode RFID Mode selection see Table 6 7 NFC 0 Passive mode 1 Active mode B2 iso_2 RFID protocol Card Emulation RFID Mode selection NFC 0 NFC normal modes 1 Card emulation mode B1 iso_1 RFID pr...

Page 26: ...h bit rate double subcarrier 1 out of 4 0 0 1 1 1 ISO IEC 15693 high bit rate double subcarrier 1 out of 256 0 1 0 0 0 ISO IEC 14443 A bit rate 106 kbps 0 1 0 0 1 ISO IEC 14443 A high bit rate 212 kbps RX bit rate when TX rate different from RX rate see register 0x03 0 1 0 1 0 ISO IEC 14443 A high bit rate 424 kbps 0 1 0 1 1 ISO IEC 14443 A high bit rate 848 kbps 0 1 1 0 0 ISO IEC 14443 B bit rate...

Page 27: ... level can be read after the end of each receive packet The RSSI register values are reset with every transmission TX by the reader This ensures an updated RSSI measurement for each new tag response The Internal RSSI has 7 steps 3 bit with a typical increment of approximately 4 dB The operating range is between 600 mVPP and 4 2 VPP with a typical step size of approximately 600 mV Both Internal Mai...

Page 28: ... command 0x0F values range from 0x40 to 0x7F 5 Repeat steps 1 to 4 as needed The register is reset when it is read 6 6 Oscillator Section The 13 56 MHz or 27 12 MHz crystal or oscillator is controlled by the Chip Status Control register 0x00 and the EN and EN2 terminals The oscillator generates the RF frequency for the RF output stage as well as the clock source for the digital section The buffere...

Page 29: ...n configured for 5 V automatic operation The transmit power levels are selectable between 33 mW half power or 70 mW full power when configured for 3 V automatic operation The ASK modulation depth is controlled by bits B0 B1 and B2 in the Modulator and SYS_CLK Control register 0x09 The ASK modulation depth range can be adjusted between 7 to 30 or 100 OOK External control of the transmit modulation ...

Page 30: ...ding a transmit command see Direct Commands section The transmission then starts when the transmit command is received NOTE If the data length is longer than the FIFO the TRF7970A notifies the external system MCU when most of the data from the FIFO has been transmitted by sending an interrupt request with a flag in the IRQ register to indicate a FIFO low or high status The external system should r...

Page 31: ...are also readily designed and certified high power HF reader modules on the market 6 10 TRF7970A IC Communication Interface 6 10 1 General Introduction The communication interface to the reader can be configured in two ways with a eight line parallel interface D0 D7 plus DATA_CLK or with a 4 wire Serial Peripheral Interface SPI The SPI interface uses traditional Master Out Slave In MOSI Master In ...

Page 32: ... last two columns of Table 6 11 show the function of the separate bits if either address or command is written Data is expected once the address word is sent In continuous address mode Cont mode 1 the first data that follows the address is written or read to from the given address For each additional data the address is incremented by one Continuous mode can be used to write to a block of control ...

Page 33: ...6 8 summarizes the continuous address mode communication Figure 6 8 and Figure 6 9 show the signals between the MCU and the TRF7970A Table 6 12 Continuous Address Mode Start Adr x Data x Data x 1 Data x 2 Data x 3 Data x 4 Data x n StopCont Figure 6 8 Continuous Address Register Write Example Starting With Register 0x00 Using SPI With SS Figure 6 9 Continuous Address Register Read Example Starting...

Page 34: ...s Mode Table 6 13 summarizes the noncontinuous address single address mode communication Figure 6 10 and Figure 6 11 show the signals between the MCU and the TRF7970A Table 6 13 Noncontinuous Address Mode Single Address Mode Start Adr x Data x Adr y Data y Adr z Data z StopSgl Figure 6 10 Single Address Register Write Example of Register 0x00 Using SPI With SS Figure 6 11 Single Address Register R...

Page 35: ...two counters and three FIFO status flags The first counter is a 7 bit FIFO byte counter bits B0 to B6 in register 0x1C that tracks the number of bytes loaded into the FIFO If the number of bytes in the FIFO is n the register value is n number of bytes in FIFO register For example if 8 bytes are in the FIFO the FIFO counter Register 0x1C has the hexadecimal value of 0x08 binary value of 00001000 A ...

Page 36: ...y The MCU must also validate the number of data bytes to be sent so as to not surpass the value defined in the TX Length Byte registers 0x1D and 0x1E The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception Figure 6 13 shows an example of checking the FIFO Status register using SPI with SS Figure 6 13 Example of Checking the FIFO Stat...

Page 37: ...evels register 0x14 An IRQ_FIFO interrupt request is sent to the MCU during the receive operation if the data string is greater than the level set in the Adjustable FIFO IRQ Levels register 0x14 After receiving an IRQ_FIFO or RX complete interrupt the MCU must read the FIFO Status register 0x1C to determine the number of bytes to be read from the FIFO Next the MCU must read the data in the FIFO It...

Page 38: ...cation SPI When an SPI interface is used I O pins I O_2 I O_1 and I O_0 must be hard wired according to Table 6 10 On power up the TRF7970A looks for the status of these pins and then enters into the corresponding mode The serial communications work in the same manner as the parallel communications with respect to the FIFO except for the following condition On receiving an IRQ from the reader the ...

Page 39: ...Links TRF7970A Detailed Description Copyright 2011 2017 Texas Instruments Incorporated Figure 6 17 Procedure for Dummy Read Figure 6 18 Example of Dummy Read Using SPI With SS 6 10 5 1 Serial Interface Mode With Slave Select SS The serial interface is in reset while the Slave Select signal is high Serial data in MOSI changes on the rising edge and is validated in the reader on the falling edge as ...

Page 40: ...www ti com Submit Documentation Feedback Product Folder Links TRF7970A Detailed Description Copyright 2011 2017 Texas Instruments Incorporated Figure 6 19 SPI With Slave Select Timing Diagram The read command is sent out on the MOSI pin MSB first in the first eight clock cycles MOSI data changes on the rising edge and is validated in the reader on the falling edge as shown in Figure 6 19 During th...

Page 41: ...egisters in this example are configured for 5 VDC in and default operation Figure 6 22 Inventory Command Sent From MCU to TRF7970A The TRF7970A takes these bytes from the MCU and then send out Request Flags Inventory Command and Mask over the air to the ISO IEC 15693 transponder After these three bytes have been transmitted an interrupt occurs to indicate back to the reader that the transmission h...

Page 42: ... and occurs in this example approximately 4 ms after first IRQ is read and cleared In the continuation of the example see Figure 6 24 the IRQ Status Register is read using method previously recommended followed by a single read of the FIFO Status register which indicates that there are 10 bytes to be read out Figure 6 24 Read IRQ Status Register After Inventory Command This is then followed by a c...

Page 43: ...2017 Texas Instruments Incorporated Figure 6 25 Continuous Read of FIFO After Inventory Command TI recommends resetting the FIFO after receiving data Additionally the RSSI value of the tag can be read out at this point In the example in Figure 6 26 the transponder is very close to the antenna so value of 0x7F is recovered Figure 6 26 Reset FIFO and Read RSSI ...

Page 44: ...hat has the same bit coding as one of the protocols implemented in the reader but needs a different framing format To select direct mode the user must first choose which direct mode to enter by writing B6 in the ISO Control register This bit determines if the receive output is the direct subcarrier signal B6 0 or the serial data of the selected decoder If B6 1 then the user must also define which ...

Page 45: ... or 1 for OOK Step 3 Program the TRF7970A registers The following registers must be explicitly set before going into the direct mode 1 ISO Control register 0x01 to the appropriate standard 0x02 for ISO IEC 15693 High Data Rate 0x08 for ISO IEC 14443 A 106 kbps 0x1A for FeliCa 212 kbps 0x1B for FeliCa 424 kbps 2 Modulator and SYS_CLK register 0x09 to the appropriate clock speed and modulation 0x21 ...

Page 46: ...nt that the last write is not terminated with a stop condition For SPI this means that Slave Select I O_4 stays low Sending a Stop condition terminates the direct mode and clears bit B6 in the Chip Status Control register 0x00 NOTE Access to Registers FIFO and IRQ is not available during direct mode 0 The reader enters the direct mode 0 when bit 6 of the Chip Status Control register 0x00 is set to...

Page 47: ...and no IRQs are generated See the applicable ISO standard to understand bit and frame definitions Figure 6 30 shows an example of what the developer sees when using DM0 in an actual application This figure clearly shows the relationship between the MOD pin being controlled by the MCU and the resulting modulated 13 56 MHz carrier signal Figure 6 30 TX Sequence Out in DM0 Step 6 Receive Data Using D...

Page 48: ...ce Y Carrier for 9 44 µs Sequence Z Pause for 2 Carrier for Remainder of 9 44 to 3 µs µs 48 TRF7970A SLOS743L AUGUST 2011 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links TRF7970A Detailed Description Copyright 2011 2017 Texas Instruments Incorporated Figure 6 31 Receive Data Bits and Framing Level ...

Page 49: ...A perform these steps 1 Raise the EN EN2 and SS lines at the correct intervals after power up for timing diagrams see Figure 6 3 and Figure 6 4 2 Issue a Software Initialization direct command 0x03 followed by an Idle direct command 0x00 to soft reset the TRF7970A NOTE Table 6 21 lists the initial register settings for the TRF7970A after the Software Initialization command 3 Delay 1 ms to allow th...

Page 50: ...06 kbps passive target SDD B6 Id_s0 B5 Sdd_en 1 Enables internal SDD protocol Automatic SDD using internal state machine and ID stored in NFCID Number register 1 B4 N A B3 Hi_rf Extended range for RF measurements B2 Rfdet_h2 RF field level required for system wake up If all bits are 0 the RF level detection is switched off Comparator output is displayed in NFC Target Protocol register B7 rf_h B1 R...

Page 51: ...CU handles the SDD and the command received is send to FIFO If the RF field is turned off B7 in the NFC Target Protocol register goes low at any time the system sends an IRQ to the MCU with bit B2 RF field change in the IRQ register set high This informs the MCU that the procedure was aborted and the system must be reset The clock extractor is automatically activated in this mode If the command is...

Page 52: ...bps Collision error bit can also be triggered by external noise B0 Irq_noresp No response time interrupt No response within the No response time defined in RX No response Wait Time register 0x07 Signals the MCU that next slot command can be sent Only for ISO IEC 15693 6 13 2 Initiator The chip is fully controlled by the MCU as in RFID reader operation The MCU activates the chip and writes the mode...

Page 53: ...s if the word is to be used as a command or address The last two columns of Table 6 20 show the function of each bit depending on whether address or command is written Command mode is used to enter a command resulting in reader action initialize transmission enable reader and turn reader on or off 6 14 1 1 Idle 0x00 This command issues dummy clock cycles In parallel mode one cycle is issued In SPI...

Page 54: ...protocol 0x00 0x1A Test 0x00 0x1B Test 0x00 0x1C FIFO status 0x00 6 14 1 3 Initial RF Collision Avoidance 0x04 See the TRF7970A Errata 6 14 1 4 Response RF Collision Avoidance 0x05 See the TRF7970A Errata 6 14 1 5 Response RF Collision Avoidance 0x06 n 0 See the TRF7970A Errata 6 14 1 6 Reset FIFO 0x0F The reset command clears the FIFO contents and FIFO Status register 0x1C It also clears the regi...

Page 55: ...part of the receiver if the reset mode was entered by the block receiver command 6 14 1 14 Test Internal RF RSSI at RX Input With TX ON 0x18 The level of the RF carrier at RF_IN1 and RF_IN2 inputs is measured Operating range between 300 mVP and 2 1 VP step size is 300 mV The two values are displayed in the RSSI Levels and Oscillator Status register 0x0F The command is intended for diagnostic purpo...

Page 56: ... After power up and the EN pin low to high transition the reader is in the default mode The default configuration is ISO IEC 15693 single subcarrier high data rate 1 out of 4 operation The low level option registers 0x02 to 0x0B are automatically set to adapt the circuitry optimally to the appropriate protocol parameters When entering another protocol by writing to the ISO Control register 0x01 th...

Page 57: ...n 6 15 3 2 8 0x0A RX special setting R W Section 6 15 3 2 9 0x0B Regulator and I O control R W Section 6 15 3 2 10 0x10 Special function register preset 0x00 R W Section 6 15 3 3 4 0x11 Special function register preset 0x00 R W Section 6 15 3 3 5 0x14 Adjustable FIFO IRQ levels R W Section 6 15 3 3 6 0x15 Reserved R W 0x16 NFC low field level R W Section 6 15 3 3 7 0x17 NFCID1 number up to 10 byte...

Page 58: ... Half output power TX_OUT pin 5 8 Ω output impedance P 100 mW 20 dBm at 5 V P 33 mW 15 dBm at 3 3 V 0 Full output power TX_OUT pin 5 4 Ω output impedance P 200 mW 23 dBm at 5 V P 70 mW 18 dBm at 3 3 V B3 pm_on 1 Selects aux RX input RX_IN2 input is used 0 Selects main RX input RX_IN1 input is used B2 Reserved B1 rec_on 1 Receiver activated for external field measurement Forced enabling of receiver...

Page 59: ...ubcarrier 1 out of 4 Default for reader 0 0 0 1 1 ISO IEC 15693 high bit rate 26 48 kbps one subcarrier 1 out of 256 0 0 1 0 0 ISO IEC 15693 low bit rate 6 67 kbps double subcarrier 1 out of 4 0 0 1 0 1 ISO IEC 15693 low bit rate 6 67 kbps double subcarrier 1 out of 256 0 0 1 1 0 ISO IEC 15693 high bit rate 26 69 kbps double subcarrier 1 out of 4 0 0 1 1 1 ISO IEC 15693 high bit rate 26 69 kbps do...

Page 60: ...e 0 EGT after last byte is omitted B0 Auto SDD_SAK 1 ISO IEC 14443 A Layer 4 compliant in SAK response 0 Not Layer 4 compliant in SAK response For use with Auto SDD configuration makes B6 in ISO IEC 14443 A response 1 or 0 indicating Layer 4 compliance or not for all other cases this bit is unused 6 15 3 2 2 ISO IEC 14443 High Bit Rate and Parity Options Register 0x03 Table 6 30 describes the ISO ...

Page 61: ... Condition B5 tm_lengthD Timer Length MSB B4 tm_lengthC Timer Length B3 tm_lengthB Timer Length B2 tm_lengthA Timer Length B1 tm_length9 Timer Length B0 tm_length8 Timer Length LSB 6 15 3 2 4 TX Timer Low Byte Control Register 0x05 Table 6 32 describes the TX Timer Low Byte Control register Table 6 32 TX Timer Low Byte Control Register 0x05 Function For Timings Default 0x00 at POR H or EN L and at...

Page 62: ...EC 14443 A at 848 kbps pulse length control disabled B6 Pul_p1 B5 Pul_p0 B4 Pul_c4 B3 Pul_c3 B2 Pul_c2 B1 Pul_c1 B0 Pul_c0 Pulse length LSB 6 15 3 2 6 RX No Response Wait Time Register 0x07 The RX No Response timer is controlled by the RX NO Response Wait Time Register 0x07 This timer measures the time from the start of slot in the anticollision sequence until the start of tag response If there is...

Page 63: ...write to ISO Control register 0x01 according to the minimum tag response time defined by each standard Table 6 35 describes the RX Wait Time register Table 6 35 RX Wait Time Register 0x08 Function Defines the time after TX EOF when the RX input is disregarded for example to block out electromagnetic disturbance generated by the responding card Default 0x1F at POR H or EN L and at each write toISO ...

Page 64: ...s the modulation input and depth ASK OOK control and clock output to external system MCU Default 0x91 at POR H or EN L and at each write to ISO control register except Clo1 and Clo0 Bit Name Function Description B7 27MHz Enables 27 12 MHz crystal Default 1 enabled B6 en_ook_p 1 Enables external selection of ASK or OOK modulation 0 Default operation as defined in B0 to B2 0x09 Enable ASK OOK pin pi...

Page 65: ... 570 kHz Appropriate for 212 kHz subcarrier system FeliCa B6 C424 Band pass 200 kHz to 900 kHz Appropriate for 424 kHz subcarrier used in ISO IEC 15693 B5 M848 Band pass 450 kHz to 1 5 MHz Appropriate for Manchester coded 848 kHz subcarrier used in ISO IEC 14443 A and B B4 hbt Band pass 100 kHz to 1 5 MHz Gain reduced for 18 dB Appropriate for highest bit rate 848 kbps used in high bit rate ISO IE...

Page 66: ...voltage is between 1 8 V to 2 7 V B4 Unused No function Default is 0 B3 Unused No function Default is 0 B2 vrs2 Voltage set MSB voltage set LSB Vrs3_5 L VDD_RF VDD_A VDD_X range 2 7 V to 3 4 V see Table 6 39 and Table 6 40 B1 vrs1 B0 vrs0 Table 6 39 Supply Regulator Setting Manual 5 V System REGISTER OPTION BITS SETTING IN CONTROL REGISTER ACTION B7 B6 B5 B4 B3 B2 B1 B0 00 1 5 V system 0B 0 Manual...

Page 67: ...interrupt request IRQ 1 is sent when TX is finished B6 Irg_srx IRQ set due to RX start Signals that RX SOF was received and RX is in progress The flag is set at the start of RX but the interrupt request IRQ 1 is sent when RX is finished B5 Irq_fifo Signals the FIFO level Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels 0x14 register B4 Irq_err1 CRC error Indicates receive CRC erro...

Page 68: ...1 Irq_col RF collision avoidance finished The system has finished collision avoidance and the minimum wait time is elapsed B0 Irq_col_err RF collision avoidance not finished successfully The external RF field was present so the collision avoidance could not be carried out 6 15 3 3 2 Interrupt Mask Register 0x0D and Collision Position Register 0x0E Table 6 45 describes the Interrupt Mask register T...

Page 69: ...ds section The measuring system is latching the peak value so the RSSI level can be read after the end of receive packet The RSSI value is reset during next transmit action of the reader so the new tag response level can be measured The RSSI levels calculated to the RF_IN1 and RF_IN2 are presented in Section 6 5 1 1 and Section 6 5 1 2 The RSSI has 7 steps 3 bits with 4 dB increment The input leve...

Page 70: ...ed B1 Reserved Reserved B0 irg_srx Copy of the RX start signal Bit 6 of the IRQ Status register 0x0C Signals the RX SOF was received and the RX is in progress IRQ when RX is completed 6 15 3 3 6 Adjustable FIFO IRQ Levels Register 0x14 Table 6 50 describes the Adjustable FIFO IRQ Levels register Table 6 50 Adjustable FIFO IRQ Levels Register 0x14 Function Adjusts level at which FIFO indicates stat...

Page 71: ... 7 in register 0x18 to enable SDD anticollision bit 5 and set bit 6 and 7 to select the ID length of 4 7 or 10 bytes 2 Write the ID into register 0x17 This should be done using write continuous mode with 4 7 or 10 bytes according to what was set in register 0x18 bits 6 and 7 6 15 3 3 9 NFC Target Detection Level Register 0x18 Table 6 52 describes the NFC Target Detection Level register Table 6 52 ...

Page 72: ...iously described and IRQs also fire to indicate RX is complete 0x40 This register must be checked and compared against case statement structure that is set up for the value of this register to be 0xC5 indicating that an ISO IEC 14443 B command at 106 kbps was issued When this register 0x19 is 0xC5 then the FIFO Status can be read and should hold a value of 0x03 and when read be the REQB command 0x...

Page 73: ...First stage output selection o_sel L First stage output used for analog out and digitizing o_sel H Second Stage output used for analog out and digitizing B3 low2 Second stage gain 6 dB HP corner frequency 2 B2 low1 First stage gain 6 dB HP corner frequency 2 B1 zun Input followers test B0 Test_AGC AGC test AGC level is seen on rssi_210 bits 6 15 3 4 2 Test Register 0x1B Table 6 55 describes the Te...

Page 74: ...ter 0x1C Table 6 56 FIFO Status Register 0x1C Function Number of bytes available to be read from FIFO N number of bytes in hexadecimal Bit Name Function Description B7 Foverflow FIFO overflow error Bit is set when FIFO has more than 127 bytes presented to it B6 Fb6 FIFO bytes fb 6 Bits B0 B6 indicate how many bytes are in the FIFO to be read out N number of bytes in hex B5 Fb5 FIFO bytes fb 5 B4 F...

Page 75: ...e byte bn 8 B3 Txl7 Number of complete byte bn 7 Middle nibble of complete intended bytes to be transmitted B2 Txl6 Number of complete byte bn 6 B1 Txl5 Number of complete byte bn 5 B0 Txl4 Number of complete byte bn 4 Table 6 58 TX Length Byte2 Register 0x1E Function Low nibbles of complete bytes to be transferred through FIFO Information about a broken byte and number of bits to be transferred f...

Page 76: ... interference The recommended clock frequency on the DATA_CLK line is 2 MHz This figure also shows matching to a 50 Ω port which allows connecting to a properly matched 50 Ω antenna circuit or RF measurement equipment for example a spectrum analyzer or power meter 7 1 2 Schematic Figure 7 1 shows a sample application schematic for SPI with an SS mode MCU interface Figure 7 1 Application Schematic ...

Page 77: ... this Avoid crossing of digital lines under RF signal lines Also avoid crossing of digital lines with other digital lines when possible If the crossings are unavoidable 90 crossings should be used to minimize coupling of the lines Depending on the production test plan consider possible implementations of test pads or test vias for use during testing The necessary pads or vias should be placed in a...

Page 78: ...hing Circuit Figure 7 3 Smith Chart Simulation Resulting power out can be measured with a power meter or spectrum analyzer with power meter function or other equipment capable of making a hot measurement Observe maximum power input levels on test equipment and use attenuators whenever available to avoid damage to equipment Expected output power levels under various operating conditions are shown i...

Page 79: ...ully qualified production devices with no prefix Device development evolutionary flow xTRF Experimental device that is not necessarily representative of the electrical specifications of the final device pTRF Final device that conforms to the electrical specifications of the final product but has not completed quality and reliability verification TRF Fully qualified production device Devices with a...

Page 80: ...cation of documentation updates including silicon errata go to the product folder for your device on ti com for example TRF7970A In the upper right corner click the Alert me button This registers you to receive a weekly digest of product information that has changed if any For change details check the revision history of any revised document Errata TRF7970A Silicon Errata Describes the known excep...

Page 81: ...ctive contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Community TI s Engineer to Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers 8 6 Trademarks E2E is a trademark of Texas Instruments Blue...

Page 82: ... Texas Instruments Incorporated 9 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation ...

Page 83: ...uirements of 1000ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature 4 There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 5 Mul...

Page 84: ...PACKAGE OPTION ADDENDUM www ti com 6 Feb 2020 Addendum Page 2 ...

Page 85: ... Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant TRF7970ARHBR VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 TRF7970ARHBT VQFN RHB 32 250 180 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 PACKAGE MATERIALS INFORMATION www ti com 27 Jul 2015 Pack Materials Page 1 ...

Page 86: ... Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TRF7970ARHBR VQFN RHB 32 3000 367 0 367 0 35 0 TRF7970ARHBT VQFN RHB 32 250 210 0 185 0 35 0 PACKAGE MATERIALS INFORMATION www ti com 27 Jul 2015 Pack Materials Page 2 ...

Page 87: ...VIEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RHB 32 PLASTIC QUAD FLATPACK NO LEAD 5 x 5 0 5 mm pitch 4224745 A ...

Page 88: ...32 25 OPTIONAL PIN 1 ID 0 1 C A B 0 05 C EXPOSED THERMAL PAD 33 SYMM SYMM NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance SCALE 3 000 SEE S...

Page 89: ...kage is designed to be soldered to a thermal pad on the board For more information see Texas Instruments literature number SLUA271 www ti com lit slua271 5 Vias are optional depending on application refer to device data sheet If any vias are implemented refer to their locations shown on this view It is recommended that vias under paste be filled plugged or tented 33 SOLDER MASK OPENING METAL UNDER...

Page 90: ...D 4223442 B 08 2019 NOTES continued 6 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 33 SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 33 75 PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE 20X SYMM 1 8 9 16 17 24 25 32 ...

Page 91: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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