Texas Instruments TPS65941515-Q1 User Manual Download

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User’s Guide

User Guide for Powering Jacinto

7 J7200 DRA821 with

Single TPS6594-Q1 PMIC, PDN-2A

ABSTRACT

This User’s Guide can be used as a guide for integrating the TPS65941515-Q1 power management integrated
circuit (PMIC) into a system powering the Automotive Jacinto™ 7 DRA821 processor.

Table of Contents

1 Introduction

.............................................................................................................................................................................

2 Device Versions

......................................................................................................................................................................

3 Processor Connections

..........................................................................................................................................................

3.1 Power Mapping..................................................................................................................................................................

3.2 Control Mapping.................................................................................................................................................................

4 Supporting Functional Safety Systems

................................................................................................................................

4.1 Achieving ASIL-B System Requirements.........................................................................................................................

4.2 Achieving up to ASIL-D System Requirements................................................................................................................

5 Static NVM Settings

..............................................................................................................................................................

5.1 Application-Based Configuration Settings........................................................................................................................

5.2 Device Identification Settings...........................................................................................................................................

5.3 BUCK Settings.................................................................................................................................................................

5.4 LDO Settings....................................................................................................................................................................

5.5 VCCA Settings.................................................................................................................................................................

5.6 GPIO Settings..................................................................................................................................................................

5.7 Finite State Machine (FSM) Settings...............................................................................................................................

5.8 Interrupt Settings..............................................................................................................................................................

5.9 POWERGOOD Settings...................................................................................................................................................

5.10 Miscellaneous Settings..................................................................................................................................................

5.11 Interface Settings............................................................................................................................................................

5.12 Watchdog Settings.........................................................................................................................................................

6 Pre-Configurable Finite State Machine (PFSM) Settings

..................................................................................................

6.1 Configured States............................................................................................................................................................

6.2 PFSM Triggers.................................................................................................................................................................

6.3 Power Sequences............................................................................................................................................................

7 Application Examples

..........................................................................................................................................................

7.1 Moving Between States: ACTIVE and RETENTION........................................................................................................

7.2 Entering and Exiting Standby...........................................................................................................................................

7.3 Entering and Existing LP_STANDBY...............................................................................................................................

7.4 GPIO8 and Watchdog......................................................................................................................................................

8 References

............................................................................................................................................................................

Trademarks

Jacinto

™

is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

www.ti.com

Table of Contents

SLVUCD4 – NOVEMBER 2022

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User Guide for Powering Jacinto

7 J7200 DRA821 with Single TPS6594-Q1

PMIC, PDN-2A

Summary of Contents for TPS65941515-Q1

Page 1: ...5 4 LDO Settings 15 5 5 VCCA Settings 16 5 6 GPIO Settings 16 5 7 Finite State Machine FSM Settings 18 5 8 Interrupt Settings 19 5 9 POWERGOOD Settings 21 5 10 Miscellaneous Settings 22 5 11 Interface Settings 23 5 12 Watchdog Settings 23 6 Pre Configurable Finite State Machine PFSM Settings 24 6 1 Configured States 25 6 2 PFSM Triggers 27 6 3 Power Sequences 28 7 Application Examples 35 7 1 Movin...

Page 2: ...ent versions of the TPS6594 Q1 device available with unique NVM settings to support different processor solutions The unique NVM settings for each PMIC device are optimized per PDN design to support different processors processing loads SDRAM types system functional safety levels and end product features such as low power modes processor voltages and memory subsystems The NVM settings can be ident...

Page 3: ...ending upon end product features The two TPS22965 Q1 Load Switches connect VCCA_3V3 power rail to supply 3 3 V to processor I O domains The third discrete device is a TPS274501 Q1 LDO is used to supply power in low power retention mode The fourth discrete device is a TLV73318 Q1 LDO which supplies the LPDDR4 SDRAM component with required 1 8V supply The last discrete power component is an optional...

Page 4: ...G VDDA_0P8_PHYs VDDA_0P8_PLLs DLLs VDDA_1P8_PLLs VDDA_3P3_USB VDDSHV0 MAIN DIGITAL VDDSHV2 VDDSHV5 VDDS_MMC0 VPP_x EFUSE Octal SPI FLASH Hyper FLASH EMMC VCC VCCQ VDD_CPU_AVS VDD_CORE_0V8 VDD_DDR_1V1 VDD_RAM_0V85 VDA_LN_1V8 VDD_IO_1V8 VDA_DPLL_0V8 VDD_IO_3V3 VDD_WK_0V85 VPP_EFUSE_1V8 VDD_GPIORET_3V3 VDD1_LPDDR4_1V8 VCCA_3V3 TPS22965 Q1 Load switch 4A max TLV73318P Q1 LDO 300mA max TLV73318P Q1 LDO...

Page 5: ...D2 and VDDQ LDO1 VDD_IO_1 V8 VDDS_MMC0 VDDSHVx_MCU 1 8V R Mem VCC LDO2 VDD_RAM _0V85 VDDAR_MCU VDDAR_CPU CORE R LDO3 VDA_DPLL _0V8 VDDA_0P8_PLLs DLLs R LDO4 VDA_LN_1 V8 VDDA_x 1 8V R TPS22965 Q1 Load Switch A VDD_IO_3 V3 VDDSHVx_MCU 3 3 V VDDSHV0 VDDSHV5 R R R Mem EMMC VCC TPS22965 Q1 Load Switch B VDD_GPIO RET_3V3 VDDSHV0 4 VDDSHV6 3 3 V R R TPS74501 P Q1 LDO A VDD_WK_ 0V8 VDDSHV2 R R TLV73318P Q...

Page 6: ...ey signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational The digital connections shown in Figure 3 2 allow system features including GPIO and DDR Retention modes functional safety up to ASIL D and compliant dual voltage SD card operation Processor Connections www ti com 6 User Guide for Powering JacintoTM 7 J7200 DRA821 with Single TPS6594 ...

Page 7: ...n PMIC_WAKE H_MCU_SAFETY_ERRn PMIC_GPIO81 EN_GPIORET_VIO H_WKUP_LFOSCO_XI EN_SOC_VIO EN_GPIORET_VWK EN_DDR_RET_1V1 Power Processor Group Processor Sub group Processor Supply Groups System Group System IO Domain Descriptors VCCA VRTC 1 8V VINT 1 8V VIO 1 8V or 3 3V PMIC IO Domain PDN Options Base PDN Retention TPS22965 Q1 TLV73318P Q1 EN_EFUSE_VPP3 Figure 3 2 TPS65941515 Q1 Digital Connections 1 PM...

Page 8: ...function does not cause any conflicts with normal operations for example two outputs driving same net For details on how functional safety related connections help achieve functional safety system level goals see Section 4 Table 3 3 Digital Connections by System Feature Device GPIO Mapping System Features 1 PMIC Pin NVM Function PDN Signals Active SoC Functional Safety DDR Retention GPIO Retention...

Page 9: ...t provides an independent path to disable system actuators Error Pin Monitoring Internal Diagnostics including voltage monitoring temperature monitoring and Built In Self Test Refer to the Safety Manual of the TPS6594 Q1 device for full descriptions and analysis of the PMIC functional safety features These functional safety features can assist in achieving up to ASIL D rating for a system Addition...

Page 10: ...the system An example of re purposing GPIO_8 is provided in Section 7 4 GPIO_7 is configured as the MCU error signal monitor but must be enabled though the ESM_MCU_EN register bit MCU reset is supported through the connection between the primary PMIC nRSTOUT pin and the MCU_PORz of the processor Lastly there are two I2C ports between the TPS6594 Q1 and the processor The first is used for all non w...

Page 11: ... Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage or current monitoring since other means are available for example SoC internal timeout gaskets and ECC checkers provide diagnostic coverage to detect faults in the DDR voltage 3 Power rails VDD_IO_1V8 3V3 is typically not safety critical since other means are available for example black channel chec...

Page 12: ...also have optimal output inductance values that optimize the performance of each buck under these various conditions Table 5 1 shows the default configurations for the BUCKs These settings cannot be changed after device startup Table 5 1 Application Use Case Settings Device BUCK Rail Default Application Use Case Recommended Inductor Value TPS65941515 Q1 BUCK1 4 4 MHz VOUT Less than 1 9 V Single Ph...

Page 13: ...regulator BUCK1_FPWM 0x0 PFM and PWM operation AUTO mode BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding BUCK1_VMON_EN 0x0 Disabled OV UV SC and ILIM comparators BUCK1_VSEL 0x0 BUCK1_VOUT_1 BUCK1_PLDN 0x1 Enabled Pull down resistor BUCK1_RV_SEL 0x1 Enabled BUCK1_CONF BUCK1_SLEW_RATE 0x3 5 0 mV μs BUCK1_ILIM 0x5 5 5 A BUCK2_CTRL BUCK2_EN 0x0 Disabled BUCK2 regulator BUCK2_FPWM 0x0 PFM and PWM...

Page 14: ...UCK1_VOUT_1 BUCK1_VSET1 0x37 0 800 V BUCK1_VOUT_2 BUCK1_VSET2 0x37 0 800 V BUCK2_VOUT_1 BUCK2_VSET1 0x37 0 800 V BUCK2_VOUT_2 BUCK2_VSET2 0x37 0 800 V BUCK3_VOUT_1 BUCK3_VSET1 0x37 0 800 V BUCK3_VOUT_2 BUCK3_VSET2 0x37 0 800 V BUCK4_VOUT_1 BUCK4_VSET1 0x37 0 800 V BUCK4_VOUT_2 BUCK4_VSET2 0x37 0 800 V BUCK5_VOUT_1 BUCK5_VSET1 0x73 1 10 V BUCK5_VOUT_2 BUCK5_VSET2 0x73 1 10 V BUCK1_PG_WINDOW BUCK1_O...

Page 15: ...tors LDO2_RV_SEL 0x1 Enabled LDO3_CTRL LDO3_EN 0x0 Disabled LDO3 regulator LDO3_SLOW_RAMP 0x0 25mV us max ramp up slew rate for LDO output from 0 3V to 90 of LDO3_VSET LDO3_PLDN 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled OV and UV comparators LDO3_RV_SEL 0x1 Enabled LDO4_CTRL LDO4_EN 0x0 Disabled LDO4 regulator LDO4_SLOW_RAMP 0x0 25mV us max ramp up slew rate for LDO output from 0 3V to 90 of LDO4_VSET...

Page 16: ... output GPIO1_DIR 0x0 Input GPIO1_SEL 0x1 SCL_I2C2 CS_SPI GPIO1_PU_SEL 0x0 Pull down resistor selected GPIO1_PU_PD_EN 0x0 Disabled Pull up pull down resistor GPIO1_DEGLITCH_EN 0x0 No deglitch only synchronization GPIO2_CONF GPIO2_OD 0x0 Push pull output GPIO2_DIR 0x0 Input GPIO2_SEL 0x2 SDA_I2C2 SDO_SPI GPIO2_PU_SEL 0x0 Pull down resistor selected GPIO2_PU_PD_EN 0x0 Disabled Pull up pull down resi...

Page 17: ...WDOG GPIO8_PU_SEL 0x0 Pull down resistor selected GPIO8_PU_PD_EN 0x1 Enabled Pull up pull down resistor GPIO8_DEGLITCH_EN 0x1 8 us deglitch time GPIO9_CONF GPIO9_OD 0x0 Push pull output GPIO9_DIR 0x1 Output GPIO9_SEL 0x0 GPIO9 GPIO9_PU_SEL 0x0 Pull down resistor selected GPIO9_PU_PD_EN 0x0 Disabled Pull up pull down resistor GPIO9_DEGLITCH_EN 0x0 No deglitch only synchronization GPIO10_CONF GPIO10...

Page 18: ...d All these settings can be changed though I2C after startup Table 5 7 FSM NVM Settings Register Name Field Name TPS65941515 Q1 Value Description RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group BUCK2_GRP_SEL 0x1 MCU rail group BUCK3_GRP_SEL 0x1 MCU rail group BUCK4_GRP_SEL 0x1 MCU rail group RAIL_SEL_2 BUCK5_GRP_SEL 0x1 MCU rail group LDO1_GRP_SEL 0x1 MCU rail group LDO2_GRP_SEL 0x1 MCU rail group LDO...

Page 19: ...Masking sets signal value to 0 FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x1 Masked GPIO9_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 GPIO10_FSM_MASK 0x1 Masked GPIO10_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 GPIO11_FSM_MASK 0x1 Masked GPIO11_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated BUCK1_OV_MASK 0x0 Interrupt generated BUCK1_...

Page 20: ...0x1 Interrupt not generated GPIO8_FALL_MASK 0x1 Interrupt not generated MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated GPIO2_RISE_MASK 0x1 Interrupt not generated GPIO3_RISE_MASK 0x1 Interrupt not generated GPIO4_RISE_MASK 0x1 Interrupt not generated GPIO5_RISE_MASK 0x1 Interrupt not generated GPIO6_RISE_MASK 0x1 Interrupt not generated GPIO7_RISE_MASK 0x1 Interrupt not generated GP...

Page 21: ...generated MASK_ESM ESM_SOC_PIN_MASK 0x1 Interrupt not generated ESM_SOC_RST_MASK 0x1 Interrupt not generated ESM_SOC_FAIL_MASK 0x1 Interrupt not generated ESM_MCU_PIN_MASK 0x1 Interrupt not generated ESM_MCU_RST_MASK 0x1 Interrupt not generated ESM_MCU_FAIL_MASK 0x1 Interrupt not generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated 5 9 POWERGOOD Settings These settings detail the default ...

Page 22: ...et to Hs mode by Hs mode controller code EN_ILIM_FSM_CTRL 0x0 Buck LDO regulator ILIM interrupts do not affect FSM triggers NSLEEP1_MASK 0x0 NSLEEP1 B affects FSM state transitions NSLEEP2_MASK 0x0 NSLEEP2 B affects FSM state transitions CONFIG_2 BB_CHARGER_EN 0x0 Disabled BB_VEOC 0x0 2 5V BB_ICHR 0x0 100uA RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf BUCK_RESET_REG BUCK1_RESET 0x0 0x0 BUCK2_RESET 0x0 0x...

Page 23: ...R_MASK 0x0 ABIST errors not masked GENERAL_REG_1 REG_CRC_EN 0x1 Register CRC enabled FAST_VCCA_OVP 0x0 Slow 4us deglitch filter enabled 5 11 Interface Settings These settings detail the default interface interface configurations and device addresses These settings cannot be changed after device startup Table 5 11 Interface NVM Settings Register Name Field Name TPS65941515 Q1 Value Description SERI...

Page 24: ...S6594 Q1 devices These settings cannot be changed after device startup Pre Configurable Finite State Machine PFSM Settings www ti com 24 User Guide for Powering JacintoTM 7 J7200 DRA821 with Single TPS6594 Q1 PMIC PDN 2A SLVUCD4 NOVEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 25: ...tionally the transitions to hardware states such as SAFE RECOVERY and LP_STANDBY are shown The hardware states are part of the fixed device power Finite State Machine FSM and described in the TPS6594 Q1 data sheet see Section 8 www ti com Pre Configurable Finite State Machine PFSM Settings SLVUCD4 NOVEMBER 2022 Submit Document Feedback User Guide for Powering JacintoTM 7 J7200 DRA821 with Single T...

Page 26: ...ion instructions are performed to disable the residual voltage checks on both the BUCK and LDO regulators and set the FIRST_STARTUP_DONE bit After these instructions are executed the PMIC waits for a valid ON Request before entering the ACTIVE state The definition for each power state is described below STANDBY The PMICs are powered by a valid supply on the system power rail VCCA VCCA_UV All devic...

Page 27: ...tate transition between configured states Table 6 1 describes each trigger and its associated state transition from highest priority Immediate Shutdown to lowest priority I2C_3 Active triggers of higher priority block triggers of lower priority and the associated sequence Table 6 1 State Transition Triggers Trigger Priority ID Immediate IMM REENTERANT PFSM Current State PFSM Destination State Powe...

Page 28: ...e mechanism to wakeup the device as determined by the means of entering LP_STANDBY Refer to the data sheet for more details 3 I2C_0 I2C_1 I2C_2 and I2C_3 are self clearing triggers 4 NSLEEP1 and NSLEEP2 of the PMIC can be accessed through the GPIO pin or through a register bit If either the register bit or the GPIO pin is pulled high the NSLEEPx value is read as a high logic level 5 After completi...

Page 29: ...E_SEVERE sequence executes the following instruction after the power sequence Clear AMUXOUT_EN CLKMON_EN set LPM_EN REG_WRITE_MASK_IMM ADDR 0x81 DATA 0x04 MASK 0xE3 The TPS65941515 has an additional delay of 500 ms at the end of the TO_SAFE_SEVERE sequence It is important to note that the recovery is not attempted until after the sequence delay is complete 6 3 2 TO_SAFE_ORDERLY and TO_STANDBY If a...

Page 30: ...EG_WRITE_MASK_IMM ADDR 0x87 DATA 0x1F MASK 0xE0 The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY state Transitioning to the SAFE_RECOVERY state means that the PMIC leaves the mission state The SAFE_RECOVERY state is where the recovery mechanism increments the recovery counter and determine if the recovery count threshold see Table 5 10 was achieved ...

Page 31: ...regulators are returned to the values stored in NVM and the recovery counter is incremented If the recovery counter exceeds the recovery count threshold the PMIC stays in the safe recovery state Note After the ACTIVE_TO_WARM sequence the MCU is responsible for managing the EN_DRV and recovery counter At the end of the sequence the FORCE_EN_DRV_LOW bit is cleared so that the MCU can set the ENABLE_...

Page 32: ..._PORz TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 TPS65941515 Q1 Resource PMIC Delay Diagram Total Delay Rail Name Figure 6 5 TO_ACTIVE Sequence At the end of the TO_ACTIVE sequence the FORCE_EN_DRV_LOW bit is cleared Note After the TO_ACTIVE sequence the MCU is responsible for managing the EN_DRV 6 3 5 TO_R...

Page 33: ...wing PMIC PFSM instructions are executed automatically in the beginning of the power sequence to configure the PMIC Clear NRSTOUT REG_WRITE_MASK_IMM ADDR 0x81 DATA 0x00 MASK 0xFE Set SPMI_LP_EN and FORCE_EN_DRV_LOW REG_WRITE_MASK_IMM ADDR 0x82 DATA 0x18 MASK 0xE7 Resource nRSTOUT TPS65941515 Q1 PMIC Delay Diagram Total Delay Rail Name 0 us H_SOC_PORz_1V8 BUCK5 TPS65941515 Q1 500 us VDD_DDR_1V1 BUC...

Page 34: ...1 1000 us VDD_CORE_0V8 LDO3 TPS65941515 Q1 1000 us VDA_DPLL_0V8 GPIO9 TPS65941515 Q1 2000 us EN_GPIORET_VIO EN_DRV TPS65941515 Q1 0 us EN_DRV Holds Level if I2C_7 1 Holds Level if I2C_6 1 Holds Level if I2C_6 1 Figure 6 7 TO_RETENTION when I2C_6 and I2C_7 are High At the end of the sequence PMIC sets the LPM_EN and clears the CLKMON_EN and AMUXOUT_EN bits Pre Configurable Finite State Machine PFSM...

Page 35: ...NSLEEP2 in TPS65941515 Write 0x48 0x66 0x01 0xFE Clear BIST_PASS_INT Write 0x48 0x65 0x26 0xD9 Clear all potential sources of the On Request 7 1 2 RETENTION As shown in TO_RETENTION the MCU is powered off and therefore the transition out of the RETENTION to the ACTIVE state must be configured before entering RETENTION The I2C_6 and I2C_7 triggers must be set depending on the type of retention mode...

Page 36: ..._STANDBY is different and requires different initializations before entering LP_STANDBY Also when the PMIC returns from LP_STANDBY the PFSM triggers are gated by the ENABLE_INT while in STANDBY the triggers were gated by the GPIO interrupt Write 0x48 0xC3 0x08 0xF7 LP_STANDBY_SEL 1 Write 0x48 0x7D 0xC0 0x3F Mask NSLEEP bits Write 0x48 0x34 0xC0 0x3F Set GPIO4 to WKUP1 goes to ACTIVE state Write 0x...

Page 37: ...Technical Reference Manual Texas Instruments TPS6594 Q1 Power Management IC PMIC with 5 Bucks and 4 LDOs for Safety Relevant Automotive Applications data sheet Texas Instruments TPS6594 Q1 Safety Manual request through mySecure Texas Instruments TPS6594 Q1 Schematic PCB Checklist application note www ti com References SLVUCD4 NOVEMBER 2022 Submit Document Feedback User Guide for Powering JacintoTM...

Page 38: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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