Table 6-1. State Transition Triggers (continued)
Trigger
Priority (ID)
Immediate
(IMM)
REENTERANT
PFSM Current State
PFSM
Destination
State
Power Sequence or
Function Executed
NSLEEP1 goes
low and
NSLEEP2 goes
low
14
False
False
ACTIVE
Suspend-to-
RAM
TO_RETENTION
NSLEEP1 goes
high and
NSLEEP2 goes
low
15
False
False
ACTIVE
Suspend-to-
RAM
I2C_0 bit goes
16
False
False
STANDBY, ACTIVE
LP_STANDBY
TO_STANDBY
I2C_3 bit goes
17
False
False
ACTIVE
No State
Change
Devices are prepared
for OTA NVM update.
(1)
From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From
the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see
RECOV_CNT_REG_2, in
). If the recovery count threshold is reached, then the PMIC halts recovery attempts and requires
a power cycle. Refer to the
for more details.
(2)
If the LP_STANDBY_SEL bit is set (see RTC_CTRL_2, in
), then the PFSM transitions to the hardware FSM state of
LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by
the means of entering LP_STANDBY. Refer to the
(3)
I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.
(4)
NSLEEP1 and NSLEEP2 of the PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the
GPIO pin is pulled high, the NSLEEPx value is read as a
high
logic level.
(5)
After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.
6.3 Power Sequences
6.3.1 TO_SAFE_SEVERE and TO_SAFE
The TO_SAFE_SEVERE and TO_SAFE are distinct sequences which occur when transition to the SAFE state.
Both sequences shut down all rails without delay. To prevent any damage of the PMIC in case of over voltage
on VCCA or thermal shutdown, the TO_SAFE_SEVERE sequence immediately ceases BUCK switching and
enables the pulldown resistors of the BUCKs and LDOs. The timing is illustrated in
. The TO_SAFE
sequence does not reset the BUCK regulators until after the regulators are turned off.
Pre-Configurable Finite State Machine (PFSM) Settings
28
User Guide for Powering Jacinto
TM
7 J7200 DRA821 with Single TPS6594-Q1
PMIC, PDN-2A
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