6.3.3 ACTIVE_TO_WARM
The ACTIVE_TO_WARM sequence can be triggered by either a watchdog or ESM_MCU error. In the event of a
trigger, the nRSTOUT signal are driven low and the recovery count (register RECOV_CNT_REG_1) increments.
Then, all BUCKs and LDOs are reset to their default voltages. The PMIC remains in the ACTIVE state.
Note
GPIOs do not reset during the sequence as shown in
At the beginning of the sequence the following instructions are executed:
// Set FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x08 MASK=0xF7
// Clear nRSTOUT
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFC
// Increment the recovery counter
REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE
Note
The watchdog or ESM error is an indication of a significant error which has taken place outside
of the PMIC. The PMIC does not actually transition through the safe recovery as with an
MCU_POWER_ERR, however, in order to maintain consistency all of the regulators are returned
to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds
the recovery count threshold the PMIC stays in the safe recovery state.
Note
After the ACTIVE_TO_WARM sequence, the MCU is responsible for managing the EN_DRV and
recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the
MCU can set the ENABLE_DRV bit.
Resource
nRSTOUT
TPS65941515-Q1
PMIC
Delay Diagram
Total Delay
Rail Name
0 us
H_SOC_PORz_1V8
BUCK5
TPS65941515-Q1
0 us
VDD_DDR_1V1
LDO2
TPS65941515-Q1
0 us
VDD_RAM_0V85
BUCK34
TPS65941515-Q1
0 us
VDD_CORE_0V8
LDO3
TPS65941515-Q1
0 us
VDA_DLL_0V8
BUCK12
TPS65941515-Q1
0 us
VDD_CPU_AVS
LDO4
TPS65941515-Q1
0 us
VDA_LN_1V8
LDO1
TPS65941515-Q1
0 us
VDD_IO_1V8
nRSTOUT
TPS65941515-Q1
2000 us
H_SOC_PORz_1V8
EN_DRV
TPS65941515-Q1
0 us
EN_DRV
Figure 6-4. ACTIVE_TO_WARM Power Sequence
Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCD4 – NOVEMBER 2022
User Guide for Powering Jacinto
TM
7 J7200 DRA821 with Single TPS6594-Q1
PMIC, PDN-2A
31
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