Texas Instruments TPS65941515-Q1, User Manual

Page: 30 / 38

Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and
FORCE_EN_DRV_LOW bits.
Resource
nRSTOUT TPS65941515-Q1
PMIC Delay Diagram Total Delay Rail Name
0 us H_SOC_PORz_1V8
BUCK5 TPS65941515-Q1 500 us VDD_DDR_1V1
BUCK12 TPS65941515-Q1 1000 us VDD_CPU_AVS
LDO4 TPS65941515-Q1 1500 us VDA_LN_1V8
LDO1 TPS65941515-Q1 1500 us VDD_IO_1V8
GPIO11 TPS65941515-Q1 2000 us EN_SOC_VIO
LDO2 TPS65941515-Q1 500 us VDD_RAM_0V85
GPIO5 TPS65941515-Q1 1000 us EN_GPIORET_VWK
GPIO6 TPS65941515-Q1 1000 us EN_DDR_RET_1V1
BUCK34 TPS65941515-Q1 1000 us VDD_CORE_0V8
LDO3 TPS65941515-Q1 1000 us VDA_DPLL_0V8
GPIO9 TPS65941515-Q1 2000 us EN_GPIORET_VIO
EN_DRV TPS65941515-Q1 0 us EN_DRV
Figure 6-3. TO_SAFE_ORDERLY and TO_STANDBY Power Sequence
At the end of the TO_SAFE_ORDERLY sequence, the PMIC waits approximately 16 ms before executing the
following instructions:
// Clear AMUXOUT_EN and CLKMON_EN and set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCKs
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0
The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY
state. Transitioning to the SAFE_RECOVERY state means that the PMIC leaves the mission state. The
SAFE_RECOVERY state is where the recovery mechanism increments the recovery counter and determine
if the recovery count threshold (see
Table 5-10 ) was achieved before attempting to recover.
At the end of the TO_STANDBY sequence, the TPS65941515 device waits approximately 16 ms before
executing the same AMUXOUT_EN, CLKMON_EN, and LPM_EN bit manipulations. The BUCKs are not reset.
After these instructions, the PMIC performs an additional check to determine if the LP_STANDBY_SEL (see
Table 5-10 ) is true. If true, then the PMIC enters the LP_STANDBY state and leave the mission state. If the
LP_STANDBY_SEL is false, then the PMIC remains in the mission state defined by STANDBY in Configured
States .
Pre-Configurable Finite State Machine (PFSM) Settings www.ti.com
30 User Guide for Powering Jacinto
TM
7 J7200 DRA821 with Single TPS6594-Q1
PMIC, PDN-2A
SLVUCD4 – NOVEMBER 2022
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