Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF // clear timer interrupt, clear bit 5
7.2 Entering and Exiting Standby
STANDBY can be entered from the ACTIVE or the RETENTION states. To stay in the mission state of
STANDBY and not enter the hardware state LP_STANDBY, the LP_STANDBY_SEL bit must be cleared.
When the ENABLE pin goes low, the TO_STANDBY sequence is triggered. When the ENABLE pin goes
high again, the destination state is dependent upon the STARTUP_DEST bits. For the TPS65941515, the
STARTUP_DEST must be set for the ACTIVE state. The TO_STANDBY sequence is also triggered by the I2C_0
trigger. When triggered from I2C_0 the PMIC can be triggered to return to the ACTIVE state by GPIO4 or the
RTC timer or alarm. In this example, I2C_0 trigger is used to enter the STANDBY state and the GPIO4 is used to
enter the ACTIVE state.
Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMIC has returned to the ACTIVE state
Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
7.3 Entering and Existing LP_STANDBY
Entering the LP_STANDBY hardware state is the same as entering STANDBY. Exiting LP_STANDBY is
different and requires different initializations before entering LP_STANDBY. Also, when the PMIC returns from
LP_STANDBY the PFSM triggers are gated by the ENABLE_INT while in STANDBY the triggers were gated by
the GPIO interrupt.
Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMIC has returned to the ACTIVE state
Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x65:0x02:0xFD // clear ENABLE_INT
7.4 GPIO8 and Watchdog
The TPS65941515 GPIO8 is configured as an input to disable the watchdog. Typically, during development this
pin is tied high, so that when the nRSTOUT bit is set WD_PWRHOLD is also set. The configuration of this pin
can be utilized for other features or functions but this requires servicing the watchdog before it expires. The
watchdog long window is 772 seconds.
Write 0x12:0x09:0x00:0xBF // Disable Watchdog
Write 0x48:0x38:0x01:0x00 // configure GPIO8 as a pushpull output
When it is time to enable and configure the watchdog, then in addition to enabling the watchdog the
WD_PWR_HOLD must be cleared.
Write 0x12:0x09:0x00:0xFB // Clear WD_PWRHOLD
Write 0x12:0x09:0x40:0xBF // Enable Watchdog
Application Examples
36
User Guide for Powering Jacinto
TM
7 J7200 DRA821 with Single TPS6594-Q1
PMIC, PDN-2A
Copyright © 2022 Texas Instruments Incorporated