Texas Instruments TPS6593-Q1 User Manual Download Page 13

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Table 4-9. Interrupt NVM Settings (continued)

Register Name

Field Name

TPS6593-Q1

Value

Description

MASK_GPIO9_11 /
MASK_GPIO9_10

GPIO9_FALL_MASK

0x0

Interrupt generated

GPIO9_RISE_MASK

0x0

Interrupt generated

GPIO10_FALL_MASK

0x0

Interrupt generated

GPIO11_FALL_MASK

0x0

Interrupt generated

GPIO10_RISE_MASK

0x0

Interrupt generated

GPIO11_RISE_MASK

0x0

Interrupt generated

MASK_STARTUP

NPWRON_START_MASK

0x1

Interrupt not generated.

ENABLE_MASK

0x0

Interrupt generated

FSD_MASK

0x1

Interrupt not generated.

SOFT_REBOOT_MASK

0x1

Interrupt not generated.

MASK_MISC

TWARN_MASK

0x0

Interrupt generated

BIST_PASS_MASK

0x1

Interrupt not generated.

EXT_CLK_MASK

0x0

Interrupt generated

MASK_MODERATE_ERR

BIST_FAIL_MASK

0x1

Interrupt not generated.

REG_CRC_ERR_MASK

0x1

Interrupt not generated.

SPMI_ERR_MASK

0x1

Interrupt not generated.

NPWRON_LONG_MASK

0x1

Interrupt not generated.

PFSM_ERR_MASK

0x0

Interrupt generated

MASK_FSM_ERR

IMM_SHUTDOWN_MASK

0x0

Interrupt generated

MCU_PWR_ERR_MASK

0x0

Interrupt generated

SOC_PWR_ERR_MASK

0x0

Interrupt generated

ORD_SHUTDOWN_MASK

0x0

Interrupt generated

MASK_COMM_ERR

COMM_FRM_ERR_MASK

0x1

Interrupt not generated.

COMM_CRC_ERR_MASK

0x1

Interrupt not generated.

COMM_ADR_ERR_MASK

0x1

Interrupt not generated.

I2C2_CRC_ERR_MASK

0x1

Interrupt not generated.

I2C2_ADR_ERR_MASK

0x1

Interrupt not generated.

MASK_READBACK_ERR

EN_DRV_READBACK_ MASK

0x1

Interrupt not generated.

NINT_READBACK_MASK

0x0

Interrupt generated

NRSTOUT_READBACK_ MASK

0x0

Interrupt generated

NRSTOUT_SOC_
READBACK_MASK

0x1

Interrupt not generated.

MASK_ESM

ESM_SOC_PIN_MASK

0x1

Interrupt not generated.

ESM_SOC_RST_MASK

0x1

Interrupt not generated.

ESM_SOC_FAIL_MASK

0x1

Interrupt not generated.

ESM_MCU_PIN_MASK

0x1

Interrupt not generated.

ESM_MCU_RST_MASK

0x1

Interrupt not generated.

ESM_MCU_FAIL_MASK

0x1

Interrupt not generated.

4.9 POWERGOOD Settings

These settings detail the default configurations for what is monitored by PGOOD pin. All these settings can be
changed though I

C after startup.

www.ti.com

Static NVM Settings

SLVUC24 – MAY 2021

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Programmable PMICs: TPS6593-Q1 Default Configuration for TPS6593EVM

Summary of Contents for TPS6593-Q1

Page 1: ...Application Based Configuration Settings 4 4 2 Device Identification Settings 5 4 3 BUCK Settings 5 4 4 LDO Settings 7 4 5 VCCA and VMON Settings 8 4 6 GPIO Settings 8 4 7 Finite State Machine FSM Settings 10 4 8 Interrupt Settings 11 4 9 POWERGOOD Settings 13 4 10 Miscellaneous Settings 14 4 11 Interface Settings 15 4 12 Multi Device Settings 15 4 13 Watchdog Settings 15 5 Pre Configurable Finite...

Page 2: ...MIC systems These NVM settings are also supported in the Scalable PMICs GUI under the template name Generic_TPS6593 For more details on viewing NVM templates in the GUI see the Scalable PMIC s GUI User s Guide 3 Default Configuration This section details how the TPS6593 Q1 power resources and GPIO signals are configured by default Figure 3 1 shows that the PMIC can take 3 3 V through 5 V as its in...

Page 3: ...Ground for no interface CRC Rising edge will enable I2C SPI CRC Ground for I2C1 address 0x28 Rising edge will change I2C1 address to 0x2C Only Required if using SPI to configure or program the device LDOVRTC PMIC VOLTAGE DOMAINS VRTC VINT Required Signals GND GND I2C SDA 3 3V I2C SCL CS SDO GND Op onal I2C SPI Select CRC Enable I2C address Figure 3 1 Default Configration of TPS6593 Q1 www ti com D...

Page 4: ... supplied to support I2C or SPI communication during programming If VIO is normally enabled or supplied by an output of the PMIC either a regulator or GPIO it is recommended to externally supply VIO while making NVM updates All regulators and GPIOs excluding SPI communication on GPIO1 and GPIO2 are automatically disabled during NVM programming 4 Static NVM Settings The TPS6593 Q1 device consists o...

Page 5: ...ettings These settings detail the default voltages configurations and monitoring of the BUCK rails All these settings except switching frequency can be changed though I2C after startup Table 4 4 BUCK NVM Settings Register Name Field Name TPS6593 Q1 Value Description BUCK1_CTRL BUCK1_EN 1 0x0 Disabled BUCK1 regulator BUCK1_FPWM 0x1 PWM operation only BUCK1_FPWM_MP 0x0 Automatic phase adding and she...

Page 6: ... SC and ILIM comparators BUCK5_VSEL 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull down resistor BUCK5_RV_SEL 0x0 Disabled BUCK5_CONF BUCK5_SLEW_RATE 0x3 5 0 mV μs BUCK5_ILIM 0x2 2 5 A BUCK1_VOUT_1 BUCK1_VSET1 0x0 0 3 V BUCK1_VOUT_2 BUCK1_VSET2 0x0 0 3 V BUCK2_VOUT_1 BUCK2_VSET1 0x0 0 3 V BUCK2_VOUT_2 BUCK2_VSET2 0x0 0 3 V BUCK3_VOUT_1 BUCK3_VSET1 0x0 0 3 V BUCK3_VOUT_2 BUCK3_VSET2 0x0 0 3 V BUCK4_VO...

Page 7: ...PLDN 0x2 250 Ω LDO1_RV_SEL 0x0 Disabled LDO2_CTRL LDO2_EN 1 0x0 Disabled LDO2 regulator LDO2_SLOW_RAMP 0x0 25 mV us max ramp up slew rate for LDO output from 0 3V to 90 of LDOn_VSET LDO2_VMON_EN 0x0 Disabled OV and UV comparators LDO2_PLDN 0x2 250 Ω LDO2_RV_SEL 0x0 Disabled LDO3_CTRL LDO3_EN 1 0x0 Disabled LDO3 regulator LDO3_SLOW_RAMP 0x0 25 mV us max ramp up slew rate for LDO output from 0 3 V t...

Page 8: ...AL_REG_0 FAST_VCCA_OVP 0x0 slow 4us deglitch filter enabled VCCA_VMON_CTRL VMON_DEGLITCH_SEL 0x0 4 us VCCA_VMON_EN 0x0 Disabled OV and UV comparators VCCA_PG_WINDOW VCCA_OV_THR 0x7 10 VCCA_UV_THR 0x7 10 VCCA_PG_SET 0x0 3 3 V 4 6 GPIO Settings These settings detail the default configurations of the GPIO rails All these settings can be changed though I2C after startup Note the contents of the GPIOx_...

Page 9: ...0 GPIO5 GPIO5_PU_SEL 0x0 Pull down resistor selected GPIO5_PU_PD_EN 0x0 Disabled Pull up pull down resistor GPIO5_DEGLITCH_EN 0x0 No deglitch only synchronization GPIO6_CONF GPIO6_OD 0x0 Push pull output GPIO6_DIR 0x0 Input GPIO6_SEL 0x0 GPIO6 GPIO6_PU_SEL 0x0 Pull down resistor selected GPIO6_PU_PD_EN 0x0 Disabled Pull up pull down resistor GPIO6_DEGLITCH_EN 0x0 No deglitch only synchronization G...

Page 10: ...NABLE ENABLE_PU_SEL 0x0 Pull down resistor selected ENABLE_PU_PD_EN 0x1 Enabled Pull up pull down resistor ENABLE_DEGLITCH_EN 0x1 8 us deglitch time when ENABLE 50 ms deglitch time when NPWRON ENABLE_POL 0x0 Active high NRSTOUT_OD 0x1 Open drain output GPIO_OUT_1 GPIO1_OUT 1 0x0 Low GPIO2_OUT 1 0x0 Low GPIO3_OUT 1 0x0 Low GPIO4_OUT 1 0x0 Low GPIO5_OUT 1 0x0 Low GPIO6_OUT 1 0x0 Low GPIO7_OUT 1 0x0 ...

Page 11: ...ot masked GPIO1_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 GPIO2_FSM_MASK 0x0 Not masked GPIO2_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 GPIO3_FSM_MASK 0x0 Not masked GPIO3_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 GPIO4_FSM_MASK 0x0 Not masked GPIO4_FSM_MASK_POL 0x0 Low Masking sets signal value to 0 FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x0 Not masked GPIO5_FSM_MASK_POL 0x0...

Page 12: ...generated MASK_LDO3_4 LDO3_OV_MASK 0x1 Interrupt not generated LDO3_UV_MASK 0x1 Interrupt not generated LDO4_OV_MASK 0x1 Interrupt not generated LDO4_UV_MASK 0x1 Interrupt not generated LDO3_ILIM_MASK 0x1 Interrupt not generated LDO4_ILIM_MASK 0x1 Interrupt not generated MASK_VMON VCCA_OV_MASK 0x1 Interrupt not generated VCCA_UV_MASK 0x1 Interrupt not generated MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x...

Page 13: ...t generated SOC_PWR_ERR_MASK 0x0 Interrupt generated ORD_SHUTDOWN_MASK 0x0 Interrupt generated MASK_COMM_ERR COMM_FRM_ERR_MASK 0x1 Interrupt not generated COMM_CRC_ERR_MASK 0x1 Interrupt not generated COMM_ADR_ERR_MASK 0x1 Interrupt not generated I2C2_CRC_ERR_MASK 0x1 Interrupt not generated I2C2_ADR_ERR_MASK 0x1 Interrupt not generated MASK_READBACK_ERR EN_DRV_READBACK_ MASK 0x1 Interrupt not gen...

Page 14: ...Value Description PLL_CTRL EXT_CLK_FREQ 0x0 1 1 MHz CONFIG_1 TWARN_LEVEL 0x0 130C TSD_ORD_LEVEL 0x0 140C I2C1_HS 0x0 Standard fast or fast by default can be set to Hs mode by Hs mode master code I2C2_HS 0x0 Standard fast or fast by default can be set to Hs mode by Hs mode master code EN_ILIM_FSM_CTRL 0x0 Buck LDO regulators ILIM interrupts do not affect FSM triggers NSLEEP1_MASK 0x0 NSLEEP1 B affe...

Page 15: ... Register Name Field Name TPS6593 Q1 Value Description SERIAL_IF_CONFIG I2C_SPI_SEL 0x0 I2C I2C1_SPI_CRC_EN 0x0 CRC disabled I2C2_CRC_EN 0x0 CRC disabled I2C1_ID_REG I2C1_ID 0x28 0x28 I2C2_ID_REG I2C2_ID 0x12 0x12 4 12 Multi Device Settings These settings detail whether the device is a operating as a master or slave in the system These settings cannot be changed after device startup Table 4 13 Mul...

Page 16: ... supply on the system power rail VCCA VCCA_UV and waiting for a start up event or condition All device resources are powered down in the STANDBY state If no changes are needed from the default interface settings then the device can be re programmed in STANDBY state ACTIVE The PMIC is powered by a valid supply and has received a start up event such as ENABLE pin asserted high The PMIC will keep the...

Page 17: ...error is removed before the next startup 5 3 Power Sequences Since this NVM is intended as a starting point for programmable applications none of the power sequences include any change of output resources except for the TO_SAFE_SEVERE sequence As shown in Figure 3 this sequence will shut down all power rails in the event that any were enabled through I2C or SPI All other power sequences consist of...

Page 18: ...S6593 Q1 0 us BUCK5 LDO1 TPS6593 Q1 0 us LDO1 LDO2 TPS6593 Q1 0 us LDO2 LDO3 TPS6593 Q1 0 us LDO3 LDO4 TPS6593 Q1 0 us LDO4 Figure 5 2 TO_SAFE_SEVERE Sequence Pre Configurable Finite State Machine PFSM Settings www ti com 18 Programmable PMICs TPS6593 Q1 Default Configuration for TPS6593EVM SLVUC24 MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 19: ...Power Management IC PMIC for Processors with 5 Bucks and 4 LDOs user s guide Texas Instruments TPS6594 BOOSTXL user s guide Texas Instruments TPS6594 Q1 Schematic PCB Checklist Texas Instruments TPS6594EVM and TPS6593EVM user s guide www ti com References SLVUC24 MAY 2021 Submit Document Feedback Programmable PMICs TPS6593 Q1 Default Configuration for TPS6593EVM 19 Copyright 2021 Texas Instruments...

Page 20: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 21: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 22: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 23: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 24: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 25: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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