Texas Instruments TPS59650EVM-753, User Manual

Page: 54 / 73

1
1
1
1 1
1
1
1
9
1
1
1
1 1 1
1
1
1
1 1
1
1
1
1
R66
R45
1
1
1
1
1
R91
162k
R74
17.8k
R79
162k
17.8k R64
17.8k
R50
R46
162k
33nF C1
18
33nF C1
15
33nF C108 C104 33nF
R49
0
R44
1
1 1
1 C1
13
1
C
111
1
1
C103
1
1
C1
14
1
C1
10
1
TP5
0
TP4
9
R83
R47
9
0
R76
0
R73
0
R54
0
R58
R82
1
R86
17.8k
R56
162k R68
162k
R42
17.8k
C1
12
33nF
R67
C1
16
C1
19
C105 C107
C1
17
C120
C106
R89
R55
R69
R63
0
R93
0
R85
Not
u
sed
T
o
controller
R92 28.7k
RT
6
100k
RT
5
100k R59
28.7k RT
3
100k
R90
R88
TP5
6
TP5
5
0
R75
R78
R77
TP5
4
TP5
2
TP5
1
C109
TP4
8
T
o
processor
R80
10
R81
J8
R72
10
T
o
processor
J6
T
o
controller
J9
J7
R84 28.7k
RT
7
100k
R48
28.7k
RT
4
100k
R70
28.7k
R87
0
TP5
3 TP4
7
R62
R52
10
R61
10
R60
0
R87,
R93
=
0
for
DCR
sense
R88,
R90
=
0
for
Resistor
Sense
R75,
R85
=
0
for
DCR
sense
R77,
R78
=
0
for
Resistor
Sense
R71
0
R65,
R71
=
0
for
DCR
sense
R66,
R67
=
0
for
Resistor
Sense
R65
0
R57
0
R51
R43,
R49
=
0
for
DCR
sense
R44,
R45
=
0
for
Resistor
Sense
Current
Feedback
S
e
lection
and
Filtering
Dif
ferential
V
o
ltage
Feedback
and
termination
A
phase
c
an
be
disabled
by
pulling
th
e
c
orresponding
xCSPx
pin
to
3.3V.
Default
s
etting
for
C
PU:
3
phase
operation
Dafault
s
etting
for
G
P
U
:
2
phase
operation
CPU: Phase
disable
can
b
e
done
in
revers
e
o
rder
.Phase
3
,
then
2,
then
1.
1.
CPU
3
P
hase
operation:
R47,
R55,
R69
open
2.
CPU
2
P
hase
o
peration:
R69
u
sed
0ohm
3.
CPU
1
P
hase
o
peration:
R47,
R55
u
sed
0ohm
GPU
:
1.
G
P
U
2
P
hase
o
peration:
R83,
R89
open
2.
G
P
U
1
P
hase
operation:
R89
u
sed
0ohm
R53
R51,
R60
=
0
for
DCR
sense
R53,
R57
=
0
for
Resistor
Sense
R43
0