CH1: CSW1
CH2: CSW2
TPS59650EVM
CPU Output Load Releas with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH3: CSW3
CH4: 1.05V core
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH1: CSW1
CH2: CSW2
CH4: 1.05V core
CH3: CSW3
Performance Data and Typical Characteristic Curves
www.ti.com
Figure 15. CPU3 Output Load Insertion with OSR/USR
Figure 16. CPU3 Output Load Release with OSR/USR
middle level
middle level
Figure 17. CPU3 Bode Plot at 12Vin, 1.05V/60A
Test condition: CPU3 12Vin, 1.05V/60A no airflow
20
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU
SLUU896 – March 2012
SVID Power System
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