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Texas Instruments TPS59650EVM-753, User Manual

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Texas Instruments TPS59650EVM-753 User Manual Download Page 16

Test Procedure

www.ti.com

Figure 6. TPS59650EVM-753 GPU GUI set up Window

6. Measure V3: GPU Vcore_G at J9 and A1: 12VBAT input current

7. Vary GPU LOAD from 0Adc to 50Adc, GPU Vcore must remain in load line

8. Vary 12VBAT from 9V to 20V GPU Vcore must remain in line regulation

9. Push S4 to “OFF” position to disable GPU Vcore controller.

10. Decrease LOAD to 0A and disconnect the LOAD from terminal J11

11. Disconnect V3 from J9.

12. Disconnect scope probe from TP46

13. Exit SVID GUI window: click File

→

click Exit

14. Disconnect the USB cable between host Computer and EVM

16

Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU

SLUU896 – March 2012

SVID Power System

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Summary of Contents for TPS59650EVM-753

Page 1: ...USB Cable Connections 10 4 5 Input Connections 10 4 6 Output Connections 11 5 Configuration 11 5 1 CPU and GPU Configuration 11 5 2 1 2VDDQ 0 6V VTT and 0 6V VTTREF Configuration 13 5 3 1 05V VCCIO C...

Page 2: ...PU2 Dynamic VID SetVID Decay Fast 22 28 CPU2 Output Load Insertion with OSR USR middle level 23 29 CPU2 Output Load Release with OSR USR middle level 23 30 CPU2 Bode Plot at 12Vin 1 05V 55A 24 31 CPU2...

Page 3: ...cy 36 75 1 05V Load regulation 36 76 1 05V Enable Turn on 36 77 1 05V Enable Turn off 36 78 1 05V Switching Node 37 79 1 05V Ripple 37 80 1 05V Transient DCM TO CCM 37 81 1 05V Transient CCM to DCM 37...

Page 4: ...ode Selection 12 6 5Vin Bias Voltage Option J33 12 7 On Board Dynamic Load Selection 12 8 VR_ON Enable Selection 13 9 VDDQ S3 S5 Enable Selection 13 10 1 05V Enable Selection 13 11 VCCIO Output Voltag...

Page 5: ...V 20V Input Intel IMVP7 SVID Power System GUI communication to demonstrate full IMVP7 Mobile feature 3 Phase CPU Vcore can support up to 94A output current 2 Phase GPU Vcore can support up to 46A outp...

Page 6: ...Board Dynamic Load for CPU GPU and VCCIO CPU 0A 32A SVID 5Vin 3 3V 250mA Host Computer B USB Cable A GUI communication DDR3L DDR4 Memory Rail TPS59650EVM 753 Power System Block Diagram www ti com 2 TP...

Page 7: ...n 4 5 5 5 5 V Maximum input current VBAT 12 V all full load 0 3 A No load input current VBAT 12V all no load 0 1 A OUTPUT CHARACTERISTICS CPU TPS59650 Output voltage Vcore SVID Address 00 CPU Payload...

Page 8: ...ent 0 10 A Output over current 16 A Switching frequency Selectable 500 kHz Full load efficiency VBAT 12V 1 05V 10A 89 87 DDR3L DDR4 Memory Rail TPS51916 Output voltage 1 2 V Line regulation 0 1 Output...

Page 9: ...Bandwidth AC coupling 2us division horizontal resolution 50mV division vertical resolution Test point TP30 and TP46 can be used to measure the output ripple voltage for CPU and GPU Do not use a leade...

Page 10: ...nt from 5Vin to 1A maximum Make sure 5Vin is initially set to 0V and connected as shown in Figure 4 2 Prior to connecting the 12VBAT DC source it is advisable to limit the source current from 12VBAT t...

Page 11: ...1 2 pin shorted 150k Max 2nd 3 4 pin shorted 100k Level 7 3rd 5 6 pin shorted 75k Level 6 4th 7 8 pin shorted 56 2k Level 5 5th 9 10 pin shorted 39 2k Level 4 6th 11 12 pin shorted 30 1k Level 3 7th...

Page 12: ...efault setting No Jumper shorts on J33 Table 6 5Vin Bias Voltage Option J33 Jumper set to Selection No Jumper 5Vin Bias from J22 external Jumper on J39 5Vin Bias from USB 5Vin from J22 should not be c...

Page 13: ...S0 ON position ON position ON ON ON S3 OFF position ON position ON ON OFF High Z S4 S5 OFF position OFF position OFF Discharge OFF Discharge OFF Discharge 5 3 1 05V VCCIO Configuration 5 3 1 1 05V En...

Page 14: ...1 to measure 5Vin input voltage 9 Increase 12VBAT from 0V to 12V Using V2 to measure 12VBAT input voltage 10 Double Click the icon to launch the GUI program The GUI window shown in Figure 5 11 Push S4...

Page 15: ...tion to enable the VR_ON of TPS59650 The VR_ON LED will light up 4 Now you are ready to send SVID commends for GPU Using pull down menu Address 01 GPU Commend SetVIDslow Payload 1 23V 5 Click send Com...

Page 16: ...on 9 Push S4 to OFF position to disable GPU Vcore controller 10 Decrease LOAD to 0A and disconnect the LOAD from terminal J11 11 Disconnect V3 from J9 12 Disconnect scope probe from TP46 13 Exit SVID...

Page 17: ...ect V3 from J20 6 1 4 VCCIO 1 Connect the LOAD to VCCIO terminal J15 and V3 at J16 Ensure correct polarity 2 Push S1 to ON position to enable the VCCIO controller VCCIO EN and PGOOD LED will light up...

Page 18: ...5V 60A CPU 3 Phase operation CH1 CSW1 CH2 CSW2 CH3 1 05V core CH4 CPGOOD Performance Data and Typical Characteristic Curves www ti com 7 Performance Data and Typical Characteristic Curves Figure 7 thr...

Page 19: ...EVM CPU Dynamic VID Set VID Fast fast TPS59650EVM CPU Dynamic VID Set VID Decay Fast Test condition 12 Vin 1 05V 1A CPU 3 Operation CH4 VDIO CH1 CSW1 CH2 CSW2 CH3 1 05V core www ti com Performance Dat...

Page 20: ...oad CH1 CSW1 CH2 CSW2 CH4 1 05V core CH3 CSW3 Performance Data and Typical Characteristic Curves www ti com Figure 15 CPU3 Output Load Insertion with OSR USR Figure 16 CPU3 Output Load Release with OS...

Page 21: ...0 55 I Output Current A O V 12 V IN V 9 V IN V 20 V IN www ti com Performance Data and Typical Characteristic Curves Figure 18 CPU3 MOSFET Figure 19 CPU3 IC 7 2 CPU 2 Phase Operation Figure 20 CPU2 Ef...

Page 22: ...tion CH4 1 05Vcore CH3 CSW2 CH2 CSW1 TPS59650EVM CPU Dynamic VID Set VID Slow Slow Test condition 12 Vin 1 05V 1A CPU 2 Operation CH1 CSW1 CH2 CSW2 CH3 1 05Vcore CH4 VDIO Performance Data and Typical...

Page 23: ...DYN_C CH3 CSW2 CH4 1 05Vcore TPS59650EVM CPU Output Load Insertion with OSR USR middle level Test condition 12 Vin 1 05V 0A 51A CPU 3 Phase on board dynamic load CH1 DYN_C CH2 CSW1 www ti com Perform...

Page 24: ...at 12Vin 1 05V 55A Test condition CPU2 12Vin 1 05V 55A no airflow Figure 31 CPU2 MOSFET Figure 32 CPU2 IC 24 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SLUU896 March 2012 SVID Pow...

Page 25: ...CH2 CSW1 CH1 VDIO CH3 1 05Vcore CH3 1 05Vcore CH1 VR_ON TPS59650EVM CPU VR_ON Turn off Test condition 12 Vin 1 05V 20A CPU 1 Phase operation CH2 CSW1 CH4 CPGOOD www ti com Performance Data and Typica...

Page 26: ...ion CH1 CSW1 CH3 1 05Vcore CH4 VDIO TPS59650EVM CPU Dynamic VID Set VID Slow Slow Test condition 12 Vin 1 05V 21A CPU 1 Operation CH1 CSW1 Performance Data and Typical Characteristic Curves www ti com...

Page 27: ...d Releas with OSR USR middle level Test condition 12 Vin 1 05V 0A 27A CPU 1 Phase on board dynamic load CH2 CSW1 CH1 DYN_C www ti com Performance Data and Typical Characteristic Curves Figure 41 CPU1...

Page 28: ...at 12Vin 1 05V 33A Test condition CPU1 12Vin 1 05V 33A no airflow Figure 45 CPU1 MOSFET Figure 46 CPU1 IC 28 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SLUU896 March 2012 SVID Pow...

Page 29: ...e operation CH2 GSW2 CH4 GPGOOD CH1 GSW1 CH3 1 23Vcore CH1 GSW1 Test condition 12 Vin 1 23V 40A GPU 2 Phase operation CH2 GSW2 CH4 GPGOOD TPS59650EVM GPU VR_ON Turn off www ti com Performance Data and...

Page 30: ...23V 1A GPU 2 Operation CH2 GSW2 TPS59650EVM GPU Dynamic VID Set VID Fast Fast CH1 GSW1 CH3 1 23Vcore_G CH4 VDIO Test condition 12 Vin 1 23V 1A GPU 2 Operation CH2 GSW2 Performance Data and Typical Cha...

Page 31: ...ase on board dynamic load CH2 GSW1 CH4 1 23Vcore CH3 GSW2 www ti com Performance Data and Typical Characteristic Curves Figure 55 GPU2 Output Load Insertion with OSR USR Figure 56 GPU2 Output Load Rel...

Page 32: ...I Output Current A O V Output Voltage V O Performance Data and Typical Characteristic Curves www ti com Figure 58 GPU2 MOSFET Figure 59 GPU2 IC 7 5 GPU 1 Phase Operation Figure 60 GPU1 Efficiency Figu...

Page 33: ...ase operation CH1 GSW1 TPS59650EVM GPU Switching Node and Output Ripple Test condition 12 Vin 1 23V 20A GPU 1 Phase operation CH2 GSW1 CH3 1 23Vcore Ripple www ti com Performance Data and Typical Char...

Page 34: ..._G TPS59650EVM GPU Output Load Insertion with OSR USR least reduction Test condition 12 Vin 1 23V 0A 18A GPU 1 Phase on board dynamic load CH2 GSW1 CH3 1 23Vcore Performance Data and Typical Character...

Page 35: ...om Performance Data and Typical Characteristic Curves Figure 70 GPU1 Output Load Release with OSR USR OFF Figure 71 GPU1 Bode Plot at 12Vin 1 23V 33A Test condition GPU1 12Vin 1 23V 33A no airflow 35...

Page 36: ...V O V 9 V IN V 20 V IN V 12 V IN Performance Data and Typical Characteristic Curves www ti com Figure 72 GPU1 MOSFET Figure 73 GPU1 IC 7 6 1 05V VCCIO Figure 74 1 05V Efficiency Figure 75 1 05V Load r...

Page 37: ...n 12 Vin 1 05VCCIO 10A CH1 VCCIO Output Ripple TPS59650EVM VCCIO Output Ripple Test condition 12 Vin 1 05VCCIO 10A www ti com Performance Data and Typical Characteristic Curves Figure 76 1 05V Enable...

Page 38: ...05VCCIO 0A 10A CH2 VCCIO Output current Performance Data and Typical Characteristic Curves www ti com Figure 80 1 05V Transient DCM TO CCM Figure 81 1 05V Transient CCM to DCM Test condition 12Vin 1 0...

Page 39: ...DDQ 8A CH2 VDDQ CH4 VDDQ_PG CH4 VDDQ_PG CH3 VTTREF CH2 VDDQ CH1 VDDQ S5 Test condition 12 Vin 1 2VDDQ 8A TPS59650EVM VDDQ S5 Turn off www ti com Performance Data and Typical Characteristic Curves 7 7...

Page 40: ...rrent CH1 VDDQ Output Test condition 12 Vin 1 2VDDQ 0A 8A TPS59650EVM VDDQ Output transient from CCM to DCM Performance Data and Typical Characteristic Curves www ti com Figure 87 1 2V Switching Node...

Page 41: ...pical Characteristic Curves Figure 91 TPS51916 Thermal 41 SLUU896 March 2012 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SVID Power System Submit Documentation Feedback Copyright 20...

Page 42: ...ard The EVM has been designed using 8 Layers circuit board with 1oz copper on outside layers Figure 92 TPS59650EVM 753 Top Layer Assembly Drawing Top view Figure 93 TPS59650EVM 753 Bottom Assembly Dra...

Page 43: ...re 94 TPS59650EVM 753 Top Copper Figure 95 TPS59650EVM 753 Bottom Copper 43 SLUU896 March 2012 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SVID Power System Submit Documentation Fee...

Page 44: ...6 TPS59650EVM 753 Internal Layer 2 Figure 97 TPS59650EVM 753 Internal Layer 3 44 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SLUU896 March 2012 SVID Power System Submit Documentatio...

Page 45: ...8 TPS59650EVM 753 Internal Layer 4 Figure 99 TPS59650EVM 753 Internal Layer 5 45 SLUU896 March 2012 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SVID Power System Submit Documentatio...

Page 46: ...0 TPS59650EVM 753 Internal Layer 6 Figure 101 TPS59650EVM 753 Internal Layer 7 46 Using the TPS59650EVM 753 Intel IMVP 7 3 Phase CPU 2 Phase GPU SLUU896 March 2012 SVID Power System Submit Documentati...

Page 47: ...0 3 C194 C197 C215 Capacitor Ceramic 0 01uF 50V X7R 10 0603 STD STD C2 C3 C4 C5 C8 C9 C10 C11 C27 C28 C29 C30 C65 C66 C67 C68 C70 28 Capacitor Ceramic 10uF 25V X7R 20 1206 STD STD C71 C72 C73 C122 C12...

Page 48: ...p 180 1 10W 1 0603 STD STD R216 R217 R222 R132 R148 R149 R150 R158 R183 R185 R205 14 Resistor Chip 10 0k 1 10W 1 0603 STD STD R214 R219 R220 R221 R230 R231 R133 R134 R151 R213 5 Resistor Chip 1 00k 1...

Page 49: ...R5 R52 R61 R72 R80 7 Resistor Chip 10 1 10W 1 0603 STD STD R143 R146 1 R6 Resistor Chip 8 25k 1 10W 1 0603 STD STD 2 R7 R22 Resistor Chip 15 4k 1 10W 1 0603 STD STD R8 R11 R14 R20 R28 14 R29 R32 R34...

Page 50: ...wer MOSFET drivers SO 8 TI UCC27324D 1 X1 Crystal controlled oscillators 0 150 x0 528 ABRACON ABLS 20 000MHZ B2 T 1 Y1 Crystal controlled oscillators 0 150 x0 528 ABRACON ABLS 12 000MHZ B2 T 1 XU1 Soc...

Page 51: ...heet 5 for FREQ selection C26 100pF 15 4k R22 R13 C22 1uF R3 See Sheet 3 for GPU Vcore TP22 C23 1uF 15 4k R7 See Sheet 5 CPU OCP selection and OSR setting 0 36uH L2 TP4 TP2 470uF C16 20 0k R16 RT2 100...

Page 52: ...C44 10uF R31 0 TP24 C45 22uF C28 10uF C46 10uF C61 10uF 1 10uF C29 C62 10uF C48 C31 1nF C49 22uF C64 10uF 1 C50 22uF C32 C34 1uF C33 TP25 TP23 TP27 0 36uH L3 22uF C51 22uF C52 C39 22uF C55 22uF TP29 C...

Page 53: ...uF TP45 TP39 C71 10uF C73 10uF 1 R40 TP41 R35 TP33 0 36uH L4 TP35 C83 TP32 TP31 C85 C86 R32 2 21 2 2uF C82 22uF C88 22uF C89 R39 2 21 22uF C92 Not used C81 C78 TP40 C96 22uF C93 C80 1uF C66 10uF GND_P...

Page 54: ...3 TP47 R62 R52 10 R61 10 R60 0 R87 R93 0 for DCR sense R88 R90 0 for Resistor Sense R75 R85 0 for DCR sense R77 R78 0 for Resistor Sense R71 0 R65 R71 0 for DCR sense R66 R67 0 for Resistor Sense R65...

Page 55: ...6 Level 5 Level 4 Level 3 Level 2 Level 1 MIN R104 2 43k Level 8 MAX Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 MIN R124 24 3k R118 56 2k R112 150k OVER CURRENT PROTECTION SELECTION OSR U...

Page 56: ...38 C124 1nF C153 330uF C129 S1 VCCIO Enable Pin To processor R145 0 R130 180 R131 180 R132 10 0k C155 C157 0 R142 R135 2 21 R134 1 00k VCCIO Power R140 0 TP69 0 42uH L6 C132 C133 330uF R144 0 GREEN D1...

Page 57: ...uF C177 C169 1 1 1nF C159 1 TP77 1 R161 0 R152 22 1k C178 TP71 TP70 C179 C181 C182 10uF R155 TP75 TP76 C167 J20 C172 0 1uF D3 GREEN R147 180 Not used R149 10 0k R150 10 0k VDDQ Power C176 10uF C173 10...

Page 58: ...O GPU and CPU Dynamic Load 1 Switch to ON position to enable the Dynamic Load 2 Switch to OFF position to disable the Dynamic Load Default R190 330 TP93 CSD16407Q5 Q14 CSD16407Q5 Q13 D4 RED 3 3V LDO C...

Page 59: ...oller 2 Switch to OFF position to Disable TPS59650 controller Default 3 01k R210 C203 0 1uF R205 10 0k Jumper to enter I2C Mode Support and Pull ups C208 1uF 330 R212 R208 0 0 R209 0 R200 1M R198 1M R...

Page 60: ...1 75 0 R224 R225 130 1 Not used R226 43 2 R223 uC Socket Main...

Page 61: ...uC Socket Others...

Page 62: ...to use 5V from USB J33 For Internal software developmenet C213 22pF 1 50k R227 TP100 USB to DSP 0 01uF C215 R230 10 0k C212 J35 NC V DP DM V J34 TP102 TP101 5V Bias option 1 Jumper shorts on J33 5V Bi...

Page 63: ...DD1A18 14 VSSA2 13 VSS1AGND 40 VDD2A18 10 VDD 15 VDDA2 26 VDDAIO 25 VSSAIO 65 VDDIO 93 VDD 59 VDD 82 VDDIO 41 VSS 62 VSS 87 VSS 84 TRST 73 TDI 68 VDD 85 VDD 3 VDDIO 46 VDDIO 42 VDD 2 VSS 11 VSS 49 VSS...

Page 64: ...246 10 0k R262 10 0k C248 0 22uF C249 220pF 5V POWER Voltage Input C243 680pF C245 1 8nF 2 GND 14 PGOOD 5 VOUT 11 MODE 9 PGND 16 VIN 17 VIN 3 COMP 6 SS 1 VCCA 4 VFB 10 IMON 13 EN 12 FSET 8 SW 7 PGND 1...

Page 65: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 66: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 67: ...oduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulation...

Page 68: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 69: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 70: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 71: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Page 72: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 73: ...All semiconductor products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable...

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