2
Caution:
long wiring connections can cause the converter to act irregularly. This can show up as pulse width
jitter or an oscillatory effect on the ripple voltage. If this condition occurs, check the set up and make adjustments.
Please see section 5.3.2 in this users guide.
2.2.2 SIMULTANEOUS TRACKING (J3)
The EVM is equipped to provide the ability to demonstrate the tracking feature of the TPS40100. In addition, the
module can be configured to have multiple TPS40100-EVMs track. The voltage tracking function allows the
TPS40100 to track an external ramp (provided on EVM). This tracking feature allows single or multiple modules to
track an external ramp in order to comply with the demands of many microprocessor and memory applications.
Please see section 5.3.3 of the test setup section of the users guide.
2.2.3 ENABLE (SW2)
The EVM is equipped with an enable/disable switch. Please see section 5.3.4 in test set up section of the users
guide. Closing S1 will disable the device by pulling the UVLO pin of the TPS40100 low. Opening the S1 will
enable the device, provided that the appropriate input voltage is present. J3 pin 4 is an enable monitor pin
providing a connection for user observation.
2.2.4 MARGIN UP/DOWN (J4)
The margin up and down feature of the EVM provides the user with the ability to trim or margin the output of the
converter up/down by 3% or 5%. EVM is equipped with convenient jumper settings to give the user the ability to
trim the output voltage. Please see section 5.3.5 in the test set up section of this users guide for more detailed
test setup information.
2.2.5 POWER GOOD (J1)
The EVM contains a power good pin to provide the user with a “power ok” signal. This pin is pulled up through a
resistor to the 5VBP pin of the TPS40100. If any of the following conditions occur the power good pin will pull low;
•
Soft-start is active (Vss < 3.5V)
•
Tracking is active (Vtrackout>.7V)
•
Vfb < 0.61V
•
Vfb > 0.77V
•
Vuvlo < 1.33V
•
Overcurrent
condition
exists
•
Die temperature is greater than 165°C
This pin can be monitored with an oscilloscope to observe its behavior. Please see section 5.3.6 in the test setup
section of the users guide.
2.2.6 SYNCHRONIZTION (J1)
To TPS40100-EVM can be synchronized to an external clock source of a higher frequency than that of the free
running PWM clock. This is a feature that can aid with input filter design. It is recommended that the
synchronization frequency be no more than 120% of the free running frequency. The EVM is configured to a
switching frequency of 370 kHz, so the external frequency into the synchronization pin should be no more than
470 kHz. Please see section 5.3.6 of the test setup section of this users guide.
Summary of Contents for TPS40100
Page 4: ...4 4 SCHEMATIC Figure 1 TPS40100EVM 001 Power Stage Control Schematic ...
Page 5: ...5 Figure 2 TPS40100EVM 001 Margin Control Component values are for reference only ...
Page 16: ...16 Iout 10A Figure 11 Power on from enable ...
Page 24: ...24 Figure 19 TPS40100EVM 001 Component Placement Viewed from Top ...
Page 25: ...25 Figure 20 TPS40100EVM 001 Silkscreen Viewed from Top ...
Page 26: ...26 Figure 21 TPS40100EVM 001 Top Copper Viewed from Top ...
Page 27: ...27 Figure 22 TPS40100EVM 001 Layer 2 X Ray View from Top ...
Page 28: ...28 Figure 23 TPS40100EVM 001 Layer 3 X Ray View from Top ...