15
5.3.4 Enable/Disable Test Set-Up
To begin testing set up EVM according to Figure 4 in the test set up section of the users guide. The switch
(ENABLE S1) provides the ability to enable and disable the device. Please see Figure 10 below for illustration.
Closing S1 will disable the device by pulling the UVLO pin of the TPS40100 low. Opening S1will enable the
device, providing that the appropriate input voltage is present. J3 pin 4 is an enable monitor pin providing a
connection for user observation.
TP1
TP2
TP16
J2
-
+
Tracking Enable
Jumper
Ma
rg
in
U
p 5%
Ma
rg
in
U
p 3%
Ma
rg
in
Do
w
n 3%
Ma
rg
in
Do
w
n 3%
1
12
9
6
11
8
5
13
10
7
4
3
2
1
Enable S1
Enable Sw itch
logic
Enable = Open
Disable = Closed
J3
15
14
4
1
2
3
Connector J3
Pin 1 Tracking In
Pin 2,3 Gnd
Pin 4 Enable Monitor
Figure 10: TPS40100EVM-001 Enable Test Set-Up Test Set-Up
Power on from enable.
Channel 1 (+3.3Vout)
Channel 3 (Power good).
Channel 4 (SS)
Vin = 12V
Summary of Contents for TPS40100
Page 4: ...4 4 SCHEMATIC Figure 1 TPS40100EVM 001 Power Stage Control Schematic ...
Page 5: ...5 Figure 2 TPS40100EVM 001 Margin Control Component values are for reference only ...
Page 16: ...16 Iout 10A Figure 11 Power on from enable ...
Page 24: ...24 Figure 19 TPS40100EVM 001 Component Placement Viewed from Top ...
Page 25: ...25 Figure 20 TPS40100EVM 001 Silkscreen Viewed from Top ...
Page 26: ...26 Figure 21 TPS40100EVM 001 Top Copper Viewed from Top ...
Page 27: ...27 Figure 22 TPS40100EVM 001 Layer 2 X Ray View from Top ...
Page 28: ...28 Figure 23 TPS40100EVM 001 Layer 3 X Ray View from Top ...