18
Vin = 12V
Iout=10A
Figure 13: Margin up 5%
5.3.6 Power Good And Synchronization Test Set-Up
The TPS40100EVM-100 has the ability to be synchronized to an external clock. To begin testing, set up EVM
according to Figure 4 in this users guide. Connector J1 contains both the power good pin and sync in pin. Power
good can be monitored for its steady state response with a DMM or with an oscilloscope to illustrate its dynamic
response. The Pgood voltage swing will range from 0 – 4.5V dependent on the condition of the output. A low on
this pin dictates a power fault and a high (4.5V) conveys “power ok”.
Pin 4 of J1 is the input for an external clock frequency. To test, set up a function generator to provide a square
wave at a frequency of above 410 kHz and below 480 kHz. Function generator should be set to provide a 0 to 5V
square wave with a 50% duty cycle. Once power is applied to the EVM, apply the external clock to the sync in pin
and observe the gate drive of the low side mosfet (Q2). This should be measured using an oscilloscope
measuring at TP7. Gate drive pulse will coincide with external clock frequency. Please see Figure 14.
Summary of Contents for TPS40100
Page 4: ...4 4 SCHEMATIC Figure 1 TPS40100EVM 001 Power Stage Control Schematic ...
Page 5: ...5 Figure 2 TPS40100EVM 001 Margin Control Component values are for reference only ...
Page 16: ...16 Iout 10A Figure 11 Power on from enable ...
Page 24: ...24 Figure 19 TPS40100EVM 001 Component Placement Viewed from Top ...
Page 25: ...25 Figure 20 TPS40100EVM 001 Silkscreen Viewed from Top ...
Page 26: ...26 Figure 21 TPS40100EVM 001 Top Copper Viewed from Top ...
Page 27: ...27 Figure 22 TPS40100EVM 001 Layer 2 X Ray View from Top ...
Page 28: ...28 Figure 23 TPS40100EVM 001 Layer 3 X Ray View from Top ...