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42
Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion
.........................................
43
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
.........................................
44
Event-Trigger Interrupt Generator
.......................................................................................
45
Event-Trigger SOCA Pulse Generator
..................................................................................
46
Event-Trigger SOCB Pulse Generator
..................................................................................
47
Simplified ePWM Module
.................................................................................................
48
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
.......................................
49
Control of Four Buck Stages. Here F
PWM1
≠
F
PWM2
≠
F
PWM3
≠
F
PWM4
....................................................
50
Buck Waveforms for (Note: Only three bucks shown here)
..........................................................
51
Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
)
..............................................................
52
Buck Waveforms for (Note: F
PWM2
= F
PWM1)
)
.............................................................................
53
Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
)
............................................................
54
Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
)
............................................................
55
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
...............................
56
3-Phase Inverter Waveforms for (Only One Inverter Shown)
.......................................................
57
Configuring Two PWM Modules for Phase Control
...................................................................
58
Timing Waveforms Associated With Phase Control Between 2 Modules
..........................................
59
Control of a 3-Phase Interleaved DC/DC Converter
..................................................................
60
3-Phase Interleaved DC/DC Converter Waveforms for
..............................................................
61
Controlling a Full-H Bridge Stage (F
PWM2
= F
PWM1)
.....................................................................
62
ZVS Full-H Bridge Waveforms
...........................................................................................
63
Time-Base Period Register (TBPRD)
...................................................................................
64
Time-Base Phase Register (TBPHS)
...................................................................................
65
Time-Base Counter Register (TBCTR)
.................................................................................
66
Time-Base Control Register (TBCTL)
..................................................................................
67
Time-Base Status Register (TBSTS)
...................................................................................
68
Counter-Compare A Register (CMPA)
.................................................................................
69
Counter-Compare B Register (CMPB)
..................................................................................
70
Counter-Compare Control Register (CMPCTL)
.......................................................................
71
Compare A High Resolution Register (CMPAHR)
...................................................................
72
Action-Qualifier Output A Control Register (AQCTLA)
...............................................................
73
Action-Qualifier Output B Control Register (AQCTLB)
...............................................................
74
Action-Qualifier Software Force Register (AQSFRC)
.................................................................
75
Action-Qualifier Continuous Software Force Register (AQCSFRC)
...............................................
76
Dead-Band Generator Control Register (DBCTL)
...................................................................
77
Dead-Band Generator Rising Edge Delay Register (DBRED)
.....................................................
78
Dead-Band Generator Falling Edge Delay Register (DBFED)
.....................................................
79
PWM-Chopper Control Register (PCCTL)
............................................................................
80
Trip-Zone Select Register (TZSEL)
....................................................................................
81
Trip-Zone Control Register (TZCTL)
..................................................................................
82
Trip-Zone Enable Interrupt Register (TZEINT)
.......................................................................
83
Trip-Zone Flag Register (TZFLG)
......................................................................................
84
Trip-Zone Clear Register (TZCLR)
....................................................................................
85
Trip-Zone Force Register (TZFRC)
....................................................................................
86
Event-Trigger Selection Register (ETSEL)
...........................................................................
87
Event-Trigger Prescale Register (ETPS)
.............................................................................
88
Event-Trigger Flag Register (ETFLG)
.................................................................................
89
Event-Trigger Clear Register (ETCLR)
................................................................................
90
Event-Trigger Force Register (ETFRC)
...............................................................................
5
SPRUG04A – October 2008 – Revised July 2009
List of Figures
© 2008–2009, Texas Instruments Incorporated