SFP
DDR3
FMC
(LPC)
FMC (HPC)
Connectivity Daughter Card
Clock Generator
and Synthesizer
CX4 Connector
USB 2.0
(Host)
12V Wall Power
12V ATX Power
USB 2.0
(Device)
Push Buttons (SW5-SW9)
MGT Port (J26-J29)
16x2 LCD Character Display
X8 PCI Express
Ethernet
System ACE
Prog (SW4)
Switch S1
Switch S2
SystemACE RST (SW3)
CPU RST (SW10)
PMBus Controller
System Monitor Headers
PMBus (J3)
GPIO DIP Switch (SW1)
MGT Clock (J30 & J31)
USB to UART (J21)
USB JTAG (J22)
Platform Flash (U27)
DVI Output
User Clock
(J55-J58)
BPI Flash (U4)
GPIO LEDs
For More InForMatIon Go to
www.xIlInx.coM/V6connKIt
This Hardware Setup Guide provides step-by-step instructions to setup the ML605 board, the FMC daughter card, and run the pre-built
Demo that uses the built-in block for PCI Express (x4Gen2 configuration), XAUI IP LogiCORE, a Virtual FIFO Memory controller interfacing
to the on-board DDR3 memory and a third-party PCIe DMA Controller.
Kit Contents
• ML605 board and FMC Connectivity Daughter Card
• CX4 Loopback Connector
• Universal 12V power supply
• 2 USB A / Mini-B cables
• 1 ethernet Cat5 cable
• 1 DVI-to-VGA adapter
• Four SMA cables
• 1 SATA cable, 1 SATA loopback cable
• 1 CompactFlash card (2GB)
• Xilinx ISE Design Suite DVDs - 11.1 and 11.4 Update
• 1 USB stick
• Fedora Core 10 Live CD
• Documents include a welcome letter, Hardware Setup Guide,
Getting Started Guide
What’s Needed for Demonstration
• Xilinx Virtex-6 FPGA Connectivity Kit
• PC system with a x8/x16 PCIe slot on the motherboard, CDROM
drive and a USB port
• Keyboard & Mouse
• Monitor
VIRTEX-6 FPGA CONNECTIVITY KIT
VIRTEX-6 FPGA CONNECTIVITY KIT
HARDwARE SETUP GUIDE
HARDwARE SETUP GUIDE
VIRTEX-6 FPGA CONNECTIVITY KIT HARDwARE SETUP GUIDE
BOARD FEATURES
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Congratulations! The Virtex-6 FPGA Connectivity Kit is now set up. The pre-built connectivity targeted reference design demonstration has
been tested, using the built-in block for PCI Express (x4 PCI Express Gen2 Endpoint), XAUI LogiCORE IP, a Virtual FIFO memory controller
designed to interface to the on-board DDR3 memory, and Northwest Logic’s high performance DMA controller for PCI Express.
Next, please refer the Getting Started Guide included in this kit. The guide provides further instructions on running the demo, evaluating and
modifying the design files – Hardware RTL design and Software Device Driver. For updated information on this Virtex-6 FPGA Connectivity
Kit, please visit
www.xilinx.com/v6connkit.
Support Information
To download Design Tools, generate license or get the latest tool updates go to www.xilinx.com/support/download.
For Technical Support, go to www.xilinx.com/support. On this site you can:
• Subscribe to Alerts on Product Technical Documentation updates
• Choose instructor-led classes and recorded e-learning options under Training
• Collaborate with the Xilinx User Community on the Forums
• Quickly scan titles of Answers Database categories through the Answer Browser
• Submit cases and report bugs online 24 hours a day through webCase
• Initiate and manage return of hardware and software products through the RMA Portal
© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners. Printed in the U.S.A. Xilinx Part Number: PN0402827-01
Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Tel: 408-559-7778
www.xilinx.com
Europe
Xilinx Europe
One Logic Drive
Citywest Business Campus
Saggart, County Dublin
Ireland
Tel: +353-1-464-0311
www.xilinx.com
Japan
Xilinx K.K.
Art Village Osaki Central
Tower 4F
1-2-2 Osaki, Shinagawa-ku
Tokyo 141-0032 Japan
Tel: +81-3-6744-7777
japan.xilinx.com
Asia Pacific Pte. Ltd.
Xilinx, Asia Pacific
5 Changi Business Park
Singapore 486040
Tel: +65-6407-3000
www.xilinx.com
STEP 10
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Performance Monitor Application: Verify Data Throughput
and Error Free Operation
A. Confirm PCIe Throughput.
B. Confirm DMA Channel throughput for the XAUI path.
C. Confirm DMA Channel throughput for the Raw Data path.
D. Confirm Error Free operation - no Buffer Descriptor Errors.
STEP 9
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Performance Monitor Application: Start Data Traffic
A. Click on Start Test to begin XAUI data transfer.
B. Click on Start Test to begin Raw data transfer.
