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ePWM Submodules

Table 6. Counter-Compare Submodule Key Signals

Signal

Description of Event

Registers Compared

CTR = CMPA

Time-base counter equal to the active counter-compare A value

TBCTR = CMPA

CTR = CMPB

Time-base counter equal to the active counter-compare B value

TBCTR = CMPB

CTR = PRD

Time-base counter equal to the active period.

TBCTR = TBPRD

Used to load active counter-compare A and B registers from the
shadow register

CTR = ZERO

Time-base counter equal to zero.

TBCTR = 0x0000

Used to load active counter-compare A and B registers from the
shadow register

2.3.3

Operational Highlights for the Counter-Compare Submodule

The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers:

1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB).

For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each
event occurs twice per cycle if the compare value is between 0x0000-TBPRD and once per cycle if the
compare value is equal to 0x0000 or equal to TBPRD. These events are fed into the action-qualifier
submodule where they are qualified by the counter direction and converted into actions if enabled. Refer
to

Section 2.4.1

for more details.

The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occur at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:

Shadow Mode:

The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE] bit and the shadow
register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow mode is enabled by
default for both CMPA and CMPB.

If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL[LOADAMODE] and
CMPCTL[LOADBMODE] register bits:

•

CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).

•

CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)

•

Both CTR = PRD and CTR = Zero

Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.

Immediate Load Mode:

If immediate load mode is selected (i.e., TBCTL[SHADWAMODE] = 1 or TBCTL[SHADWBMODE] = 1),
then a read from or a write to the register will go directly to the active register.

2.3.4

Count Mode Timing Waveforms

The counter-compare module can generate compare events in all three count modes:

•

Up-count mode: used to generate an asymmetrical PWM waveform.

•

Down-count mode: used to generate an asymmetrical PWM waveform.

•

Up-down-count mode: used to generate a symmetrical PWM waveform.

33

SPRUG04A – October 2008 – Revised July 2009

TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) Module

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© 2008–2009, Texas Instruments Incorporated

Summary of Contents for TMS320x2823x

Page 1: ...TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Reference Guide Literature Number SPRUG04A October 2008 Revised July 2009 ...

Page 2: ...2 SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 3: ... Half H Bridge HHB Converters 76 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM 78 3 7 Practical Applications Using Phase Control Between PWM Modules 82 3 8 Controlling a 3 Phase Interleaved DC DC Converter 83 3 9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter 87 4 Registers 90 4 1 Time Base Submodule Registers 90 4 2 Counter Compare Submodule Registers 94 4 3 Action...

Page 4: ... EPWMxB Outputs 40 23 Up Down Count Mode Symmetrical Waveform 43 24 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High 44 25 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 45 26 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 46 27 Up Down Count Dual Edge Symmetric Wavefo...

Page 5: ...e Base Period Register TBPRD 90 64 Time Base Phase Register TBPHS 90 65 Time Base Counter Register TBCTR 90 66 Time Base Control Register TBCTL 91 67 Time Base Status Register TBSTS 93 68 Counter Compare A Register CMPA 94 69 Counter Compare B Register CMPB 94 70 Counter Compare Control Register CMPCTL 96 71 Compare A High Resolution Register CMPAHR 97 72 Action Qualifier Output A Control Register...

Page 6: ...unter Compare B Register CMPB Field Descriptions 95 28 Counter Compare Control Register CMPCTL Field Descriptions 96 29 Compare A High Resolution Register CMPAHR Field Descriptions 97 30 Action Qualifier Output A Control Register AQCTLA Field Descriptions 97 31 Action Qualifier Output B Control Register AQCTLB Field Descriptions 98 32 Action Qualifier Software Force Register AQSFRC Field Descripti...

Page 7: ...vent Trigger Force Register ETFRC Field Descriptions 112 49 Changes for this Revision 114 7 SPRUG04A October 2008 Revised July 2009 List of Tables Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 8: ...8234 TMS320F28232 DSC Silicon Errata describes the advisories and usage notes for different versions of silicon CPU User s Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit CPU and the assembly language instructions of the TMS320C28x fixed point digital signal processors DSPs It also describes emulation features available on these DSPs SPRUEO2 ...

Page 9: ...hanced Controller Area Network eCAN Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments SPRUFZ5 TMS320x2833x 2823x Serial Communications Interface SCI Reference Guide describes the SCI which is a two wire asynchronous serial port commonly known as a UART The SCI modules support digital communications be...

Page 10: ...DC Calibration describes a method for improving the absolute accuracy of the 12 bit ADC found on the TMS320x280x and TMS320F2801x devices Inherent gain and offset errors affect the absolute accuracy of the ADC The methods described in this report can improve the absolute accuracy of the ADC to levels better than 0 5 This application report has an option to download an example program that executes...

Page 11: ...dule name is used to indicate a generic ePWM instance on a device For example output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx instance Thus EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B belong to ePWM4 1 1 Submodule Overview The ePWM module represents one complete PWM channel composed of two PWM outputs EPWMxA and EPWMxB Multiple ePWM modules are inst...

Page 12: ...hot trip on fault conditions A trip condition can force either high low or high impedance state logic levels at PWM outputs All events can trigger both CPU interrupts and ADC start of conversion SOC Programmable event prescaling minimizes CPU overhead on interrupts PWM chopping by high frequency carrier signal useful for pulse transformer gate drives Each ePWM module is connected to the input outp...

Page 13: ...1 Multiple ePWM Modules The order in which the ePWM modules are connected may differ from what is shown in Figure 1 See Section 2 2 3 3 for the synchronization scheme for a particular device Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 2 13 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePW...

Page 14: ...signals can be configured as asynchronous inputs through the GPIO peripheral Time base synchronization input EPWMxSYNCI and output EPWMxSYNCO signals The synchronization signals daisy chain the ePWM modules together Each module can be configured to either use or ignore its synchronization input The clock synchronization input and output signal are brought out to pins only for ePWM1 ePWM module 1 T...

Page 15: ...16 Phase control EPWMxTZINT CTR ZERO www ti com Introduction Figure 3 ePWM Submodules and Critical Internal Signal Interconnects Figure 3 also shows the key internal submodule interconnect signals Each submodule is described in detail in its respective section 1 2 Register Mapping The complete ePWM module control and status register set is grouped by submodule as shown in Table 1 Each register set...

Page 16: ...ters TZSEL 0x0012 1 Yes Trip Zone Select Register TZCTL 0x0014 1 Yes Trip Zone Control Register 3 TZEINT 0x0015 1 Yes Trip Zone Enable Interrupt Register 3 TZFLG 0x0016 1 Trip Zone Flag Register 3 TZCLR 0x0017 1 Yes Trip Zone Clear Register 3 TZFRC 0x0018 1 Yes Trip Zone Force Register 3 Event Trigger Submodule Registers ETSEL 0x0019 1 Event Trigger Selection Register ETPS 0x001A 1 Event Trigger P...

Page 17: ... the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Counter compare CC Specify the PWM duty cycle for output EPWMxA and or output EPWMxB Specify the time at which switching events occur on the EPWMxA or EPWMxB output Action qualifier AQ Specify the type of action taken when a time...

Page 18: ...le configurations These examples use the constant definitions shown in Example 1 These definitions are also used in the C2833x 2823x C C Header Files and Peripheral Examples SPRC530 Example 1 Constant Definitions Used in the Code Examples TBCTL Time Base Control TBCTR MODE bits define TB_COUNT_UP 0x0 define TB_COUNT_DOWN 0x1 define TB_COUNT_UPDOWN 0x2 define TB_FREEZE 0x3 PHSEN bit define TB_DISAB...

Page 19: ...Y bits define CHP1_8TH 0x0 define CHP2_8TH 0x1 define CHP3_8TH 0x2 define CHP4_8TH 0x3 define CHP5_8TH 0x4 define CHP6_8TH 0x5 define CHP7_8TH 0x6 TZSEL Trip zone Select CBCn and OSHTn bits define TZ_ENABLE 0x0 define TZ_DISABLE 0x1 TZCTL Trip zone Control TZA and TZB bits define TZ_HIZ 0x0 define TZ_FORCE_HI 0x1 define TZ_FORCE_LO 0x2 define TZ_DISABLE 0x3 ETSEL Event trigger Select INTSEL SOCASE...

Page 20: ...odule Block Diagram 2 2 1 Purpose of the Time Base Submodule You can configure the time base submodule for the following Specify the ePWM time base counter TBCTR frequency or period to control how often events occur Manage time base synchronization with other ePWM modules Maintain a phase relationship with other ePWM modules Set the time base counter to count up count down or count up and down mod...

Page 21: ...WM Extension Phase Register 1 TBPHS 0x0003 No Time Base Phase Register TBCTR 0x0004 No Time Base Counter Register TBPRD 0x0005 Yes Time Base Period Register 1 This register is available only on ePWM instances that include the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved This register is described in the device specific High Resolution Puls...

Page 22: ...t is decreasing CTR_max Time base counter equal max value TBCTR 0xFFFF Generated event when the TBCTR value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled version of the system clock SYSCLKOUT and is used by all submodules within the ePWM This clock determines the rate at which time base counter increments or decrements 2 2 3 Calcu...

Page 23: ...trategic point in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period register is the same as the active register Which register is written to or read from is determined by the TBCTL PRDLD bit This bit enables and disables the TBP...

Page 24: ...dules 4 Set TBCLKSYNC 1 2 2 3 3 Time Base Counter Synchronization A time base synchronization scheme connects all of the ePWM modules on a device Each ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ePWM modules are ...

Page 25: ...ePWMx EPWMxSYNCI SYNCI eCAP1 EPWMxSYNCO www ti com ePWM Submodules Figure 7 Time Base Counter Synchronization Scheme 1 25 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 26: ...M8SYNCI ePWM8 EPWM8SYNCO EPWM12SYNCI ePWM12 EPWM12SYNCO EPWM16SYNCI ePWM16 EPWM16SYNCO SYNCI eCAP1 ePWM Submodules www ti com Scheme 2 shown in Figure 8 is used by the 2804x devices when the ePWM pinout is configured for A channel only mode GPAMCFG EPWMMODE 3 If the 2804x ePWM pinout is configured for 280x compatible mode GPAMCFG EPWMMODE 0 then Scheme 1 is used Figure 8 Time Base Counter Synchron...

Page 27: ...ically loaded with the phase register TBPHS contents when one of the following conditions occur EPWMxSYNCI Synchronization Input Pulse The value of the phase register is loaded into the counter register when an input synchronization pulse is detected TBPHS TBCTR This operation occurs on the next valid time base clock TBCLK edge The delay from internal master module to slave modules is given by if ...

Page 28: ...tem Control and Interrupts Reference Guide listed in Related Documentation From Texas Instruments When TBCLKSYNC 0 the time base clock of all ePWM modules is stopped default When TBCLKSYNC 1 all ePWM time base clocks are started with the rising edge of TBCLK aligned For perfectly synchronized TBCLKs the prescaler bits in the TBCTL register of each ePWM module must be set identically The proper pro...

Page 29: ...BPHS value TBPRD value www ti com ePWM Submodules Figure 10 Time Base Up Count Mode Waveforms 29 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 30: ...I CTR_dir CTR zero CNT_max CTR PRD ePWM Submodules www ti com Figure 11 Time Base Down Count Mode Waveforms Figure 12 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down On Synchronization Event 30 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 31: ...hopper PC Event Trigger and Interrupt ET Trip Zone TZ GPIO MUX ADC PIE PIE www ti com ePWM Submodules Figure 13 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up On Synchronization Event 2 3 Counter Compare CC Submodule Figure 14 illustrates the counter compare submodule within the ePWM Figure 14 Counter Compare Submodule Figure 15 shows the basic structure of the counter compare submodule...

Page 32: ... qualifier submodule is configured appropriately Shadows new compare values to prevent corruption or glitches during the active PWM cycle 2 3 2 Controlling and Monitoring the Counter Compare Submodule The counter compare submodule operation is controlled and monitored by the registers shown in Table 5 Table 5 Counter Compare Submodule Registers Register Name Address Offset Shadowed Description CMP...

Page 33: ...vents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the active register and the shadow register is identical Which register is written to or read from is determined by the CMPCTL SHDWAMODE and CMPCTL SHDWBMODE bits These bits enable and disable the CMPA shadow register and CMPB shadow register respectively The behavior of the t...

Page 34: ...iming diagrams in Figure 16 through Figure 19 show when events are generated and how the EPWMxSYNCI signal interacts 34 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 35: ... EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count sequence This can lead to a compare event being skipped This skipping is considered normal operation and must be taken into account 35 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 36: ...lue CTR CMPB EPWMxSYNCI ePWM Submodules www ti com Figure 17 Counter Compare Events in Down Count Mode 36 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 37: ... Down Count Mode TBCTL PHSDIR 0 Count Down On Synchronization Event Figure 19 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 1 Count Up On Synchronization Event 2 4 Action Qualifier AQ Submodule Figure 20 shows the action qualifier AQ submodule see shaded block in the ePWM system 37 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Sub...

Page 38: ...TBCTR TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 CTR CMPA Time base counter equal to the counter compare A register TBCTR CMPA CTR CMPB Time base counter equal to the counter compare B register TBCTR CMPB Managing priority when these events occur concurrently Providing independent control of events when the time base counter is increasing and when it is decreasing 2 4 2 Action Qua...

Page 39: ...nous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC The action qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a particular event occurs The event inputs to the action qualifier submodule are further qualified by the counter direction up or down This allows for independent ...

Page 40: ...tion For clarity the drawings in this document use a set of symbolic actions These symbols are summarized in Figure 22 Each symbol represents an action as a marker in time Some actions are fixed in time zero and period while the CMPA and CMPB actions are moveable and their time positions are programmed via the counter compare A and B registers respectively To turn off or disable an action use the ...

Page 41: ...down count events will never be taken Table 10 Action Qualifier Event Priority for Up Count Mode Priority Level Event 1 Highest Software forced event 2 Counter equal to period TBPRD 3 Counter equal to CMPB on up count CBU 4 Counter equal to CMPA on up count CAU 5 Lowest Counter equal to Zero Table 11 shows the action qualifier priority for down count mode In this case the counter direction is alwa...

Page 42: ...o generate an asymmetric PWM To achieve 50 0 asymmetric PWM use the following configuration Load CMPA CMPB on period and use the period action to clear the PWM and a compare up action to set the PWM Modulate the compare value from 0 to TBPRD to achieve 50 0 PWM duty When using up count mode to generate an asymmetric PWM To achieve 0 100 asymmetric PWM use the following configuration Load CMPA CMPB...

Page 43: ...ode samples in Example 2 through Example 7 shows how to configure an ePWM module for each case Some conventions used in the figures and examples are as follows TBPRD CMPA and CMPB refer to the value written in their respective registers The active register not the shadow register is used by the hardware CMPx refers to either CMPA or CMPB EPWMxA and EPWMxB refer to the output signals from ePWMx Up ...

Page 44: ...LK counts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 200 Compare B 200 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit HSPCLKD...

Page 45: ... Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB D Actions at zero and period although appearing to occur concurrently are actually separated by one TBCLK period TBCTR wraps from period to 0000 Example 3 contains a code sample showing initialization and run time for the waveforms in Figure 25 45 SPRUG04A October 2008 Revised July 2009 T...

Page 46: ...load on TBCTR Zero EPwm1Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs AQCTLA bit PRD AQ_CLEAR EPwm1Regs AQCTLA bit CAU AQ_SET EPwm1Regs AQCTLB bit PRD AQ_CLEAR EPwm1Regs AQCTLB bit CBU AQ_SET Run Time EPwm1Regs CMPA half CMPA Duty1A adjust duty for output EPWM1A EPwm1Regs CMPB Duty1B adjust duty for output EPWM1B Figure 26 Up Count Pulse Placement Asymmetric Waveform With Inde...

Page 47: ..._DISABLE EPwm1Regs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EPwm1Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm1Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm1Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs AQCTLA bit CAU AQ_SET EPwm1Regs AQCTLA bit CBU AQ_CLEAR EPwm1Regs AQCTLB bit ZRO AQ_TO...

Page 48: ... 500 Compare B 500 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetric xEPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled xEPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EP...

Page 49: ...ts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 400 Compare B 400 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetric EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit ...

Page 50: ...m1Regs CMPA half CMPA 250 Compare A 250 TBCLK counts EPwm1Regs CMPB 450 Compare B 450 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCTR 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetric EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit HSPCLK...

Page 51: ...dule described here should be used The key functions of the dead band module are Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single EPWMxA input Programming signal pairs for Active high AH Active low AL Active high complementary AHC Active low complementary ALC Adding programmable delay to rising edges RED Adding programmable delay to falling edges FED ...

Page 52: ...er or both are applied to the input signals Polarity Control The polarity control DBCTL POLSEL allows you to specify whether the rising edge delayed signal and or the falling edge delayed signal is to be inverted before being sent out of the dead band submodule Figure 31 Configuration Options for the Dead Band Submodule Although all combinations are supported not all are typical usage modes Table ...

Page 53: ...escription S3 S2 S1 S0 1 EPWMxA and EPWMxB Passed Through No Delay X X 0 0 2 Active High Complementary AHC 1 0 1 1 3 Active Low Complementary ALC 0 1 1 1 4 Active High AH 0 0 1 1 5 Active Low AL 1 1 1 1 EPWMxA Out EPWMxA In No Delay 6 0 or 1 0 or 1 0 1 EPWMxB Out EPWMxA In with Falling Edge Delay EPWMxA Out EPWMxA In with Rising Edge Delay 7 0 or 1 0 or 1 1 0 EPWMxB Out EPWMxB In with No Delay Fig...

Page 54: ...K options are shown in Table 15 Table 15 Dead Band Delay Values in μS as a Function of DBFED and DBRED Dead Band Value Dead Band Delay in μS DBFED DBRED TBCLK SYSCLKOUT 1 TBCLK SYSCLKOUT 2 TBCLK SYSCLKOUT 4 1 0 01 μS 0 02 μS 0 04 μS 5 0 05 μS 0 10 μS 0 20 μS 10 0 10 μS 0 20 μS 0 40 μS 100 1 00 μS 2 00 μS 4 00 μS 200 2 00 μS 4 00 μS 8 00 μS 300 3 00 μS 6 00 μS 12 00 μS 400 4 00 μS 8 00 μS 16 00 μS ...

Page 55: ...rst pulse Programmable duty cycle of second and subsequent pulses Can be fully bypassed if not required 2 6 2 Controlling the PWM Chopper Submodule The PWM chopper submodule operation is controlled via the registers in Table 16 Table 16 PWM Chopper Submodule Registers mnemonic Address offset Shadowed Description PCCTL 0x001E No PWM chopper Control Register 2 6 3 Operational Highlights for the PWM ...

Page 56: ...re 34 PWM Chopper Submodule Operational Details 2 6 4 Waveforms Figure 35 shows simplified waveforms of the chopping action only one shot and duty cycle control are not shown Details of the one shot and duty cycle control are discussed in the following sections Figure 35 Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only 56 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Mo...

Page 57: ...alue from 1 to 16 Figure 36 shows the first and subsequent sustaining pulses and Table 7 3 gives the possible pulse width values for a SYSCLKOUT 100 MHz Figure 36 PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses Table 17 Possible Pulse Width Values for SYSCLKOUT 100 MHz OSHTWTHz Pulse Width hex nS 0 80 1 160 2 240 3 320 4 400 5 480 6 560 7 640 8 720 9 800 A ...

Page 58: ...le These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmable duty cycle allows a design to be tuned or optimized via software control Figure 37 shows the duty cycle control that is possible by programming the CHPDUTY bits One of seven possible duty ratios can be selected ranging from 12 5 to 87 5 Figu...

Page 59: ...accordingly when faults occur 2 7 1 Purpose of the Trip Zone Submodule The key functions of the Trip Zone submodule are Trip inputs TZ1 to TZ6 can be flexibly mapped to any ePWM module Upon a fault condition outputs EPWMxA and EPWMxB can be forced to one of the following High Low High impedance No action taken Support for one shot trip OSHT for major short circuits or over current conditions Suppo...

Page 60: ...specific version of the System Control and Interrupts Reference Guide listed in Related Documentation From Texas Instruments Each TZn input can be individually configured to provide either a cycle by cycle or one shot trip event for an ePWM module This configuration is determined by the TZSEL CBCn and TZSEL OSHTn control bits where n corresponds to the trip pin respectively Cycle by Cycle CBC When...

Page 61: ... EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state Configure the ePWM1 registers as follows TZSEL CBC5 1 enables TZ5 as a one shot event source for ePWM1 TZCTL TZA 2 EPWM1A will be forced low on a trip event TZCTL TZB 2 EPWM1B will be forced low on a trip event Conf...

Page 62: ...rip logic Trip Trip CBC trip event OSHT trip event EPWMxA EPWMxB EPWMxA EPWMxB TZCTL TZB TZCTL TZA Async Trip Set Clear TZFLG CBC TZCLR CBC Set Clear TZFLG OST ePWM Submodules www ti com Figure 39 Trip Zone Submodule Mode Control Logic 62 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments I...

Page 63: ...on for up down event qualification Uses prescaling logic to issue interrupt requests and ADC start of conversion at Every event Every second event Every third event Provides full visibility of event generation via event counters and flags Allows software forcing of Interrupts and ADC start of conversion The event trigger submodule manages the events generated by the time base submodule the counter...

Page 64: ...odule As shown in Figure 42 ADC start of conversion for all ePWM modules are ORed together and hence multiple modules can initiate an ADC start of conversion If two requests occur on one start of conversion line then only one will be recognized by the ADC Figure 42 Event Trigger Submodule Inter Connectivity of ADC Start of Conversion The event trigger submodule monitors various event conditions th...

Page 65: ...ese bits allow you to clear the flag bits in the ETFLG register via software ETFRC These bits allow software forcing of an event Useful for debugging or s w intervention A more detailed look at how the various register bits interact with the Interrupt and ADC start of conversion logic are shown in Figure 44 Figure 45 and Figure 46 Figure 44 shows the event trigger s interrupt generation logic The ...

Page 66: ...high until the ENTFLG INT flag is cleared This allows for one interrupt to be pending while one is serviced Writing to the INTPRD bits will automatically clear the counter INTCNT 0 and the counter output will be reset so no interrupts are generated Writing a 1 to the ETFRC INT bit will increment the event counter INTCNT The counter will behave as described above when INTCNT INTPRD When INTPRD 0 th...

Page 67: ...B ETSEL SOCBEN ETFLG SOCB ETSEL SOCBSEL 000 001 010 011 100 101 111 101 0 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB CTR Zero CTR PRD www ti com ePWM Submodules Figure 45 Event Trigger SOCA Pulse Generator Figure 46 shows the operation of the event trigger s start of conversion B SOCB pulse generator The event trigger s SOCB pulse generator operates the same way as the SOCA Figure 46 Event Trigger ...

Page 68: ...strobe enable EN switch closed Do nothing or ignore incoming sync strobe enable switch open Sync flow through SyncOut connected to SyncIn Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disab...

Page 69: ...rol two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated for each converter stage Figure 49 shows four buck stages each running at independent frequencies In this case all four ePWM modules are configured as Masters and no synchronization is used Figure 50 shows the waveforms generated by the setup s...

Page 70: ...r4 En EPWM4A 3 Φ X Buck 1 Vout1 Vin1 EPWM1A Buck 2 Vin2 EPWM2A Vout2 Buck 4 Buck 3 Vin3 EPWM4A Vin4 EPWM3A Vout3 Vout4 SyncIn SyncIn SyncIn Applications to Power Topologies www ti com Figure 49 Control of Four Buck Stages Here FPWM1 FPWM2 FPWM3 FPWM4 NOTE Θ X indicates value in phase register is a don t care 70 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Rev...

Page 71: ...t CB A I P I P I P I Indicates this event triggers an ADC start of conversion www ti com Applications to Power Topologies Figure 50 Buck Waveforms for Figure 49 Note Only three bucks shown here 71 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 72: ...DISABLE EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit PRD AQ_CLEAR EPwm2Regs AQCTLA bit CAU AQ_SET EPWM Module 3 config EPwm3Regs TBPRD 800 Period 801 TBCLK counts EPwm3Regs TBPHS half TBPHS 0 Set Phase register to zero EPw...

Page 73: ...e Frequencies If synchronization is a requirement ePWM module 2 can be configured as a slave and can operate at integer multiple N frequencies of module 1 The sync signal from master to slave ensures these modules remain locked Figure 51 shows such a configuration Figure 52 shows the waveforms generated by the configuration Figure 51 Control of Four Buck Stages Note FPWM2 N x FPWM1 73 SPRUG04A Oct...

Page 74: ...B CB CA CA CA CA CB CB CB CB Applications to Power Topologies www ti com Figure 52 Buck Waveforms for Figure 51 Note FPWM2 FPWM1 74 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 75: ...m2Regs TBPHS half TBPHS 0 Set Phase register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero E...

Page 76: ...trol can be extended to multiple stages Figure 53 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencies of stage 1 Figure 54 shows the waveforms generated by the configuration shown in Figure 53 Module 2 slave is configured for Sync flow through if required this configuration allows for a third Half H bridge to be controlled by PWM modul...

Page 77: ... A CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA www ti com Applications to Power Topologies Figure 54 Half H Bridge Waveforms for Figure 53 Note Here FPWM2 FPWM1 77 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 78: ..._CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit ZRO AQ_SET set actions for EPWM1A EPwm2Regs AQCTLA bit CAU AQ_CLEAR EPwm2Regs AQCTLB bit ZRO AQ_CLEAR set actions for EPWM1B EPwm2Regs AQCTLB bit CAD AQ_SET EPwm1Regs CMPA half CMPA 400 adjust duty for output EPWM1A EPWM1B EPwm1Regs CMPB 200 adjust point in time for ADCSOC trigger EPwm2Regs CMPA half CMPA 500 adjust duty for output EPWM2A EPWM2B EPwm...

Page 79: ...n EPWM3B EPWM3A Phase reg CTR CMPB CTR zero 4 Slave SyncOut X EPWM4A EPWM4B En SyncOut CTR zero CTR CMPB Phase reg Phase reg CTR CMPB CTR zero Slave 6 5 Slave X En SyncIn EPWM6B EPWM6A SyncOut X EPWM5A EPWM5B En Φ 0 Φ 0 Φ 0 Φ 0 Φ 0 SyncIn SyncIn SyncIn SyncIn SyncIn www ti com Applications to Power Topologies Figure 55 Control of Dual 3 Phase Inverter Stages as Is Commonly Used in Motor Control 79...

Page 80: ...I A P CA CA CA CA CA CA CA CA CA CA Applications to Power Topologies www ti com Figure 56 3 Phase Inverter Waveforms for Figure 55 Only One Inverter Shown 80 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 81: ...CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit OUT_MODE DB_FULL_ENABLE enable Dead band module EPwm2Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwm2Regs DBFED 50 FED 50 TBCLKs EPwm2Regs DBRED 50 RED 50 TBCLKs EPWM Module 3 config EPwm...

Page 82: ...dule section a PWM module can be configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCTR register To illustrate this concept Figure 57 shows a master and slave module with a phase relationship of 120 i e the slave leads the master Figure 57 Configuring Two PWM Modules for Phase Control Figure 58 shows the associated timing waveforms for this configuration Here TB...

Page 83: ...es of 1 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slave 3 400 Both slave modules are synchronized to the master 1 module This concept can be extended to four or more phases by setting the TBPHS values appropriately The following formula gives the TBPHS values for N phases TBPHS N M TBPRD N x 1...

Page 84: ...yncOut X EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT Φ 0 Φ 120 Φ 120 Φ 240 Applications to Power Topologies www ti com Figure 59 Control of a 3 Phase Interleaved DC DC Converter 84 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 85: ... I Z I Z I A P CA CA A P CA CA A P CA CA www ti com Applications to Power Topologies Figure 60 3 Phase Interleaved DC DC Converter Waveforms for Figure 59 85 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 86: ...CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit OUT_MODE DB_FULL_ENABLE enable Dead band module EPwm2Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi Complementary EPwm2Regs DBFED 20 FED 20 TBCLKs EPwm2Regs DBRED 20 RED 20 TBCLKs EPWM Module 3 config EPwm3Re...

Page 87: ...ched full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship between legs Such a system can be implemented by allocating the resources of two PWM modules to control a single power stage which in turn requires control of four switching elements Figure 62 shows a master slave module combination synchronized to...

Page 88: ...ZVS transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Applications to Power Topologies www ti com Figure 62 ZVS Full H Bridge Waveforms 88 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 89: ...alf TBPHS 0 Set Phase register to zero initially EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UP Asymmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Reg...

Page 90: ...er TBPHS 15 0 TBPHS R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 Time Base Phase Register TBPHS Field Descriptions Bits Name Value Description 15 0 TBPHS 0000 FFFF These bits set time base counter phase of the selected ePWM relative to the time base that is supplying the synchronization input signal If TBCTL PHSEN 0 then the synchronization event is ignored and the time bas...

Page 91: ...he up down count mode The PHSDIR bit indicates the direction the time base counter TBCTR will count after a synchronization event occurs and a new phase value is loaded from the phase TBPHS register This is irrespective of the direction of the counter before the synchronization event In the up count and down count modes this bit is ignored 0 Count down after the synchronization event 1 Count up af...

Page 92: ...es the shadow register 1 Load the TBPRD register immediately without using a shadow register A write or read to the TBPRD register directly accesses the active register 2 PHSEN Counter Register Load From Phase Register Enable 0 Do not load the time base counter TBCTR from the time base phase register TBPHS 1 Load the time base counter with the phase register when an EPWMxSYNCI input signal occurs ...

Page 93: ...his bit will clear the latched event 1 SYNCI Input Synchronization Latched Status Bit 0 Writing a 0 will have no effect Reading a 0 indicates no external synchronization event has occurred 1 Reading a 1 on this bit indicates that an external synchronization event has occurred EPWMxSYNCI Writing a 1 to this bit will clear the latched event 0 CTRDIR Time Base Counter Direction Status Bit At reset th...

Page 94: ...s ignored Clear Pull the EPWMxA and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWAMODE bit By default this register is shadowed If CMPCTL SHDWAMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LO...

Page 95: ...WMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWBMODE bit By default this register is shadowed If CMPCTL SHDWBMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADBMODE bit field determines which event will load the active register from the shadow...

Page 96: ...ble buffer All writes via the CPU access the shadow register 1 Immediate mode Only the active compare B register is used All writes and reads directly access the active register for immediate compare action 5 Reserved Reserved 4 SHDWAMODE Counter compare A CMPA Register Operating Mode 0 Shadow mode Operates as a double buffer All writes via the CPU access the shadow register 1 Immediate mode Only ...

Page 97: ...ualifier Output A Control Register AQCTLA Field Descriptions Bits Name Value Description 15 12 Reserved Reserved 11 10 CBD Action when the time base counter equals the active CMPB register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMxA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will...

Page 98: ...r Output B Control Register AQCTLB 15 12 11 10 9 8 Reserved CBD CBU R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CAD CAU PRD ZRO R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 Action Qualifier Output B Control Register AQCTLB Field Descriptions Bits Name Value Description 15 12 Reserved 11 10 CBD Action when the counter equals the active CMPB register and the counter is ...

Page 99: ...le EPWMxB output low output signal will be forced high and a high signal will be forced low Figure 74 Action Qualifier Software Force Register AQSFRC 15 8 Reserved R 0 7 6 5 4 3 2 1 0 RLDCSF OTSFB ACTSFB OTSFA ACTSFA R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 32 Action Qualifier Software Force Register AQSFRC Field Descriptions Bit Field Value Descrip...

Page 100: ...e after reset Table 33 Action qualifier Continuous Software Force Register AQCSFRC Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 2 CSFB Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure...

Page 101: ...nerator Control Register DBCTL 15 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved IN_MODE POLSEL OUT_MODE R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset 101 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated ...

Page 102: ...lso possible but not regarded as typical usage modes 00 Active high AH mode Neither EPWMxA nor EPWMxB is inverted default 01 Active low complementary ALC mode EPWMxA is inverted 10 Active high complementary AHC EPWMxB is inverted 11 Active low AL mode Both EPWMxA and EPWMxB are inverted 1 0 OUT_MODE Dead band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown i...

Page 103: ...ad only n value after reset Table 36 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions Bits Name Description 15 10 Reserved Reserved 9 0 DEL Falling Edge Delay Count 10 bit counter 4 5 PWM Chopper Submodule Control Register Figure 79 and Table 37 provide the definitions for the PWM chopper submodule control register Figure 79 PWM Chopper Control Register PCCTL 15 11 10 8 Res...

Page 104: ...00 MHz SYSCLKOUT 0010 3 x SYSCLKOUT 8 wide 240 nS at 100 MHz SYSCLKOUT 0011 4 x SYSCLKOUT 8 wide 320 nS at 100 MHz SYSCLKOUT 0100 5 x SYSCLKOUT 8 wide 400 nS at 100 MHz SYSCLKOUT 0101 6 x SYSCLKOUT 8 wide 480 nS at 100 MHz SYSCLKOUT 0110 7 x SYSCLKOUT 8 wide 560 nS at 100 MHz SYSCLKOUT 0111 8 x SYSCLKOUT 8 wide 640 nS at 100 MHz SYSCLKOUT 1000 9 x SYSCLKOUT 8 wide 720 nS at 100 MHz SYSCLKOUT 1001 ...

Page 105: ...isable TZ3 as a one shot trip source for this ePWM module 1 Enable TZ3 as a one shot trip source for this ePWM module 9 OSHT2 Trip zone 2 TZ2 Select 0 Disable TZ2 as a one shot trip source for this ePWM module 1 Enable TZ2 as a one shot trip source for this ePWM module 8 OSHT1 Trip zone 1 TZ1 Select 0 Disable TZ1 as a one shot trip source for this ePWM module 1 Enable TZ1 as a one shot trip source...

Page 106: ...nce state 01 Force EPWMxB to a high state 10 Force EPWMxB to a low state 11 Do nothing no action is taken on EPWMxB 1 0 TZA When a trip event occurs the following action is taken on output EPWMxA Which trip zone pins can cause an event is defined in the TZSEL register 00 High impedance EPWMxA High impedance state 01 Force EPWMxA to a high state 10 Force EPWMxA to a low state 11 Do nothing no actio...

Page 107: ...the user If the cycle by cycle trip event is still present when the CBC bit is cleared then CBC will be immediately set again The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCTR 0x0000 if the trip condition is no longer present The condition on the pins is only cleared when the TBCTR 0x0000 no matter where in the cycle the CBC flag is cle...

Page 108: ...0 LEGEND R W Read Write R Read only n value after resetonly an hour Table 43 Trip Zone Force Register TZFRC Field Descriptions Bits Name Value Description 15 3 Reserved Reserved 2 OST Force a One Shot Trip Event via Software 0 Writing of 0 is ignored Always reads back a 0 1 Forces a one shot trip event and sets the TZFLG OST bit 1 CBC Force a Cycle by Cycle Trip Event via Software 0 Writing of 0 i...

Page 109: ...le event time base counter equal to CMPA when the timer is incrementing 101 Enable event time base counter equal to CMPA when the timer is decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when the timer is decrementing 7 4 Reserved Reserved 3 INTEN Enable ePWM Interrupt EPWMx_INT Generation 0 Disable EPWMx...

Page 110: ...ent has occurred 10 2 events have occurred 11 3 events have occurred 9 8 SOCAPRD ePWM ADC Start of Conversion A Event EPWMxSOCA Period Select These bits determine how many selected ETSEL SOCASEL events need to occur before an EPWMxSOCA pulse is generated To be generated the pulse must be enabled ETSEL SOCAEN 1 The SOCA pulse will be generated even if the status flag is set from a previous start of...

Page 111: ...Figure 88 Event Trigger Flag Register ETFLG 15 8 Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 46 Event Trigger Flag Register ETFLG Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 SOCB Latched ePWM ADC Start of Conversion B EPWMxSOCB Status Flag 0 Indicates no EPWMxSOCB event occurred...

Page 112: ...able 48 Event Trigger Force Register ETFRC Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 SOCB SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register The ETFLG SOCB flag bit will be set regardless 0 Has no effect Always reads back a 0 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit This bit is used for test purposes 2 S...

Page 113: ...r initializing the ePWM peripheral is as follows 1 Disable global interrupts CPU INTM flag 2 Disable ePWM interrupts 3 Set TBCLKSYNC 0 4 Initialize peripheral registers 5 Set TBCLKSYNC 1 6 Clear any spurious ePWM flags including PIEIFR 7 Enable ePWM interrupts 8 Enable global interrupts 113 SPRUG04A October 2008 Revised July 2009 TMS320x2833x 2823x Enhanced Pulse Width Modulator ePWM Module Submit...

Page 114: ...tion 2 2 3 2 Added this section Time Base Clock Synchronization Global Changed all occurrences of TBCNT to TBCTR Global Changed all occurrences of DBCTL bit MODE to DBCTL bit OUT_MODE Section 4 8 Added to the sequence list Figure 90 Changed R 0 for bits 0 2 3 to R W 0 114 Revision History SPRUG04A October 2008 Revised July 2009 Submit Documentation Feedback 2008 2009 Texas Instruments Incorporated...

Page 115: ...horized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge ...

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