OMAP 2320 and the HWI Module
C-4
C.3
OMAP 2320 and the HWI Module
With the introduction of the OMAP family of dual-core ARM + ‘C55x
devices, many more interrupt sources have been defined than can be
terminated on the legacy ‘C55x level 1 interrupt controller, which has a
limit of 32 interrupts. To accommodate additional interrupt sources, a
new interrupt mechanism has been provided in hardware: the "Level 2
Interrupt Controller" (L2IC).
The additional interrupts are prioritized and multiplexed by the Level 2
Interrupt Controller onto two dedicated level 1 interrupts. DSP/BIOS
internally configures all 32 level 2 interrupts to terminate on the single
level 1 FIQ interrupt. In the 23xx/24xx OMAP family, many peripherals
that formerly interrupted the DSP at level 1 have been moved to level 2.
The DSP/BIOS interface to this interrupt controller is called the Level 2
Interrupt Manager (L2IM). The complexities of the L2IM are concealed by
reusing and enhancing existing HWI module APIs. As a result, very few
new API elements are needed.
The following sections describe extensions made to the HWI module to
support the OMAP 2320.
C.3.1
Level 2 Interrupt Controller Base Address
By default, the Level 2 Interrupt Controller (L2IC) resides at data memory
address 0x7c4800. This coincides with the reset IOMA value of 0x3e.
The IO MAP (IOMA) base address is the page index used to access DSP
I/O space addresses from DSP memory space.
If you modify IOMA for any reason, you need to tell DSP/BIOS the new
base address for the L2IC. The following Tconf configuration property is
provided for this purpose:
bios.HWI.INTC_BASE = 0x7c4800; // 0x7c4800 is default