OMAP 2420 and the HWI Module
DSP/BIOS for OMAP 2420
D-7
// valid priority values: 0-31
bios.HWI_L2_INT0.priority = 31;
// use dispatcher and enable setting iMirMask, mirmask
bios.HWI_L2_INT0.useDispatcher = true;
// setting to "bitmask" enables writing to mirmask
bios.HWI_L2_INT0.iMirMask = "bitmask";
// no other L2 interrupts while servicing HWI_L2_INT0
bios.HWI_L2_INT0.mirmask = 0xffffffff;
D.3.3
HWI_dispatchPlug API
The range of vector IDs allowed is extended from 0-31 to 0-63. The IDs
32-63 correspond to level 2 interrupts 0-31 respectively. The c55.h file
now includes definitions for C55_L2_INT0 through C55_L2_INT31,
which map to vector IDs 32-63.
The HWI_Attrs structure used by HWI_dispatchPlug has been expanded
to include a mirmask field. This field contains a 32-bit mask to specify
which additional level 2 interrupts to mask during the interrupt. Each bit
in this mask corresponds to a level 2 interrupt. The default value of
mirmask for all interrupts is to mask only the current level 2 interrupt.
typedef struct HWI_Attrs {
Uns ier0mask; // Level 1 interrupt masks
Uns ier1mask;
Arg arg; // fxn arg (default = 0)
LgUns mirmask; // Level 2 interrupt mask
} HWI_Attrs;
D.3.4
HWI_enter and HWI_exit APIs
The HWI_enter and HWI_exit assembly language macros have been
enhanced to support selective interrupt nesting control of level 2
interrupts. This matches the way level 1 interrupts are controlled.
The argument lists for these macros have an additional interrupt mask
argument. In HWI_enter, this 32-bit bitmask defines which level 2
interrupts are to be masked while executing the HWI body. In HWI_exit,
the mask defines which level 2 interrupts are to be restored to their prior
state before returning from the interrupt.
The OMAP 2420 macro invocation syntax is shown below: