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Terminal Descriptions

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2.1.4 Register Settings for Multifunction Pins

To configure the settings seen in

Table 2-1

, please see the letter/number combination in for the

appropriate registers to modify. In , the letter/number combination represents the row and the column
number from

Table 2-1

in bold type.

Please be aware that more settings may be necessary to obtain a full interface definition matching the
application requirement (e.g. register Page 0 / Register 25 to 33).

Table 2-2. Multifunction Pin Register Configuration

Required Register

Description

Required Register Setting

Description

Setting

Page 0 / Register 4, Bits D3-

Page 0 / Register 53,Bits

PLL Input on MCLK

INT2 output DOUT/MFP2

D2=00

D3-D1=101

Page 0 / Register 4, Bits D3-

INT2 output on

Page 0 / Register 55, Bits

PLL Input on BCLK

D2=01

MISO/MFP4

D4-D1=0101

Page 0 / Register 54, Bits
D2-D1=01

INT2 output on

Page 0 / Register 52, Bits

PLL Input on DIN/MFP1

Page 0 / Register 4, Bits D3-

GPIO/MFP5

D5-D2=0110

D2=11

Page 0 / Register 52, Bits

Page 0 / Register 54, Bits

D5-D2=0001

Digital Microphone Data

D2-D1=01

PLL Input on GPIO/MFP5

Page 0 / Register 4, Bits D3-

Input on DIN/MFP1

Page 0 / Register 81, Bits

D2=10

D5-D4=10

Page 0 / Register 56, Bits

Codec Clock Input on

Page 0 / Register 4, Bits D1-

Digital Microphone Data

D2-D1=01

MCLK

D0=00

Input on SCLK/MFP3

Page 0 / Register 81, Bits
D5-D4=01

Page 0 / Register 52, Bits

Codec Clock Input on

Page 0 / Register 4, Bits D1-

Digital Microphone Data

D5-D2=0001

BCLK

D0=01

Input on GPIO/MFP5

Page 0 / Register 81, Bits
D5-D4=00

Page 0 / Register 52, Bits

Codec Clock Input on

D5-D2=0001

Digital Microphone Clock

Page 0 / Register 55, Bits

GPIO/MPF5

Page 0 / Register 4, Bits D1-

Output on MISO/MFP4

D4-D1=0111

D0=10

Page 0 / Register 27, Bit

Digital Microphone Clock

Page 0 / Register 52, Bits

S BCLK input on BCLK

D3=0

Output on GPIO/MFP5

D5-D2=1010

Page 0 / Register 56, Bits

Page 0 / Register 27, Bit

Secondary I

S BCLK input

D2-D1=01

S BCLK output on BCLK

D3=1

on SCLK/MFP3

Page 0 / Register 31, Bits
D6-D5=01

Page 0 / Register 52, Bits

Page 0 / Register 27, Bit

Secondary I

S BCLK input

D5-D2=0001

S WCLK input on WCLK

D2=0

on GPIO/MFP5

Page 0 / Register 31, Bits
D6-D5=00

Page 0 / Register 56, Bits

Page 0 / Register 27, Bit

Secondary I

S WCLK in on

D2-D1=01

S WCLK output WCLK

D2=1

SCLK/MFP3

Page 0 / Register 31, Bits
D4-D3=01

Page 0 / Register 56, Bits

Page 0 / Register 52, Bits

S ADC word clock input

D2-D1=01

Secondary I

S WCLK in on

D5-D2=0001

on SCLK/MFP3

Page 0 / Register 31, Bits

GPIO/MFP50

Page 0 / Register 31, Bits

D2-D1=01

D4-D3=0

Page 0 / Register 52, Bits

Page 0 / Register 56, Bits

S ADC word clock input

D5-D2=0001

Secondary I

S DIN on

D2-D1=01

on GPIO/MFP5

Page 0 / Register 31, Bits

SCLK/MFP3

Page 0 / Register 31, Bit

D2-D1=00

D0=1

TLV320DAC3203 Application

SLAU434 – May 2012

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Summary of Contents for TLV320DAC3203

Page 1: ...TLV320DAC3203 Applications Reference Guide Literature Number SLAU434 May 2012 ...

Page 2: ... User Programmable Filters 39 2 4 3 Interpolation Filters 42 2 4 4 DAC Gain Setting 44 2 4 5 DAC Special Functions 47 2 4 6 DAC Setup 48 2 5 PowerTune 49 2 5 1 PowerTune Modes 49 2 5 2 DAC Power Consumption 51 2 6 Audio Digital I O Interface 56 2 6 1 Right Justified Mode 57 2 6 2 Left Justified Mode 58 2 6 3 I2 S Mode 59 2 6 4 DSP Mode 60 2 6 5 Secondary I2 S 61 2 7 Clock Generation and PLL 62 2 7...

Page 3: ...00 0x0F 82 5 2 16 Page 0 Register 16 Reserved Register 0x00 0x10 82 5 2 17 Page 0 Register 17 Reserved Register 0x00 0x11 82 5 2 18 Page 0 Register 18 Reserved Register 0x00 0x12 82 5 2 19 Page 0 Register 19 Reserved Register 0x00 0x13 82 5 2 20 Page 0 Register 20 ADC Oversampling AOSR Register 0x00 0x14 83 5 2 21 Page 0 Register 21 Reserved Register 0x00 0x15 83 5 2 22 Page 0 Register 22 Reserved...

Page 4: ...47 95 5 2 66 Page 0 Register 72 Beep Generator Register 2 0x00 0x48 95 5 2 67 Page 0 Register 73 Beep Generator Register 3 0x00 0x49 95 5 2 68 Page 0 Register 74 Beep Generator Register 4 0x00 0x4A 95 5 2 69 Page 0 Register 75 Beep Generator Register 5 0x00 0x4B 95 5 2 70 Page 0 Register 76 Beep Generator Register 6 0x00 0x4C 96 5 2 71 Page 0 Register 77 Beep Generator Register 7 0x00 0x4D 96 5 2 ...

Page 5: ...ents Buffer A C 0 29 0x08 0x08 0x7F 109 5 5 Page 9 Registers 109 5 5 1 Page 9 Register 0 Page Select Register 0x09 0x00 109 5 5 2 Page 9 Register 1 7 Reserved 0x09 0x01 0x07 109 5 5 3 Page 9 Register 8 15 ADC Coefficients Buffer A C 30 31 0x09 0x08 0x0F 110 5 5 4 Page 9 Register 16 31 Reserved 0x09 0x10 0x1F 110 5 5 5 Page 9 Register 32 127 ADC Coefficients Buffer A C 36 59 0x09 0x20 0x7F 110 5 6 ...

Page 6: ...lect Register 0x3E 0x00 114 5 13 2 Page 62 Register 1 7 Reserved 0x3E 0x01 0x07 114 5 13 3 Page 62 Register 8 127 DAC Coefficients Buffer B C 0 29 0x3E 0x08 0x7F 114 5 14 Page 63 Registers 114 5 14 1 Page 63 Register 0 Page Select Register 0x3F 0x00 114 5 14 2 Page 63 Register 1 7 Reserved 0x3F 0x01 0x07 114 5 14 3 Page 63 Register 8 11 DAC Coefficients Buffer B C 30 0x3F 0x08 0x0B 115 5 14 4 Page...

Page 7: ...B_P3 PRB_P6 PRB_P11 and PRB_P16 37 2 23 Signal Chain for PRB_P7 PRB_P12 PRB_P17 and PRB_P20 37 2 24 Signal Chain for PRB_P8 and PRB_P13 37 2 25 Signal Chain for PRB_P9 and PRB_P14 37 2 26 Signal Chain for PRB_P18 and PRB_P21 38 2 27 Signal Chain for PRB_P19 and PRB_P22 38 2 28 Signal Chain for PRB_P23 38 2 29 Signal Chain for PRB_P24 39 2 30 Signal Chain for PRB_P25 39 2 31 DAC Interpolation Filte...

Page 8: ...Clock Output Options 64 2 48 I2 C Write 67 2 49 I2 C Read 67 2 50 SPI Timing Diagram for Register Write 68 2 51 SPI Timing Diagram for Register Read 69 8 List of Figures SLAU434 May 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Page 9: ...on Filter A Specification 42 2 17 DAC Interpolation Filter B Specification 42 2 18 DAC Interpolation Filter C Specification 43 2 19 DRC HPF and LPF Coefficients 44 2 20 CODEC CLKIN Clock Dividers 63 2 21 Maximum TLV320DAC3203 Clock Frequencies 64 2 22 PLL_CLK Frequency Range 65 2 23 PLL Example Configurations 66 2 24 SPI Command Word 68 3 1 Input Common Mode voltage and Input Signal Swing 73 5 1 S...

Page 10: ...tialization Integrated LDO Chapter 4 Example Setups 4mm 4mm QFN and 2 7mm 2 7mm Chapter 5 Register Map and Descriptions WCSPPackage The TLV320DAC3203 sometimes referred to as the DAC3203 is a flexible low power low voltage stereo audio codec with programmable outputs PowerTune capabilities fixed predefined and parameterizable signal processing blocks integrated PLL integrated LDO and flexible digi...

Page 11: ...nment power consumption typically is less of a concern while lowest possible noise is important With PowerTune the TLV320DAC3203 can address both cases The voltage supply range for the TLV320DAC3203 for analog is 1 5V 1 95V and for digital it is 1 26V 1 95V To ease system level design a low dropout regulator LDO is integrated to generate the appropriate analog supply from input voltages ranging fr...

Page 12: ...ecific functions The PLL input for example can be programmed to be any of 4 pins MCLK BCLK DIN GPIO Table 2 1 Multifunction Pin Assignments 1 2 3 4 5 6 7 8 Pin Function MCLK BCLK WCLK DIN DOUT MFP3 MFP4 GPIO MFP1 MFP2 SCLK MISO MFP5 A PLL Input S 1 S 2 E S 3 B Codec Clock Input S 1 D 4 S 2 S 3 C I2 S BCLK input S 2 D D I2 S BCLK output E 5 E I2 S WCLK input E D F I2 S WCLK output E G I2 S ADC word...

Page 13: ...nput I E L General Purpose Input II E L General Purpose Input III E M INT1 output E E E N INT2 output E E E Q Secondary I2 S BCLK input E E R Secondary I2 S WCLK in E E S Secondary I2 S DIN E E T Secondary I2 S DOUT E U Secondary I2 S BCLK OUT E E E V Secondary I2 S WCLK OUT E E E X Aux Clock Output E E E 13 SLAU434 May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright 2012 Te...

Page 14: ... 81 Bits D5 D4 01 Page 0 Register 52 Bits Codec Clock Input on Page 0 Register 4 Bits D1 Digital Microphone Data D5 D2 0001 B2 O8 BCLK D0 01 Input on GPIO MFP5 Page 0 Register 81 Bits D5 D4 00 Page 0 Register 52 Bits Codec Clock Input on D5 D2 0001 Digital Microphone Clock Page 0 Register 55 Bits B8 P7 GPIO MPF5 Page 0 Register 4 Bits D1 Output on MISO MFP4 D4 D1 0111 D0 10 Page 0 Register 27 Bit ...

Page 15: ...4 V8 DIN MFP1 D2 D1 10 on GPIO MFP5 D5 D2 1001 Page 0 Register 56 Bits General Purpose In II on Page 0 Register 56 Bits Headset Detect Input on D2 D1 00 L6 W6 SCLK MFP3 D2 D1 10 SCLK MFP3 Page 0 Register 67 Bit D7 1 General Purpose In III on Page 0 Register 52 Bits Aux Clock Output on Page 0 Register 53 Bits L8 X5 GPIO MFP5 D5 D2 0010 DOUT MFP2 D3 D1 011 INT1 output on Page 0 Register 53 Bits Aux ...

Page 16: ...ly voltage for higher output signal swing the output common mode can be adjusted to either 1 25V 1 5V or 1 65V When the common mode voltage is configured at 1 65V and LDOIN supply is 3 3V the headphones can each deliver up to 40mW power into a 16Ω load The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog input INL and INR The analog input signals ca...

Page 17: ...d to match application requirements The voltage Vload across Rload at the beginning of slow charging should not be more than a few mV At that time the voltage across Rload can be determined as 1 For a typical Rload of 32Ω Rpop of 6 kΩ or 25 kΩ will deliver good results see Table 2 3 for register settings According to the conceptual circuit in Figure 2 3 the voltage on PAD will exponentially settle...

Page 18: ...op performance at power up 1 Choose the value of Rpop N time constants and soft stepping step time for slow power up 2 Choose the configuration for output drivers including common modes and output stage power connections 3 Select the signals to be routed to headphones 4 Power up the blocks driving signals into HPL and HPR but keep it muted 5 Unmute HPL and HPR and set the desired gain setting 6 Po...

Page 19: ...e 1 Register 125 D 1 0 as 01 would cause the offset to be calibrated for each power up of headphone This is particularly useful when some headphone configurations like gain or signal routings change between power ups Programming Page 1 Register 125 D 1 0 as 10 would cause the offset to be calibrated for only the first power up of the headphone amplifiers after hardware reset The calibration data w...

Page 20: ...d the load The cutoff frequency of the LC filter should be adjusted to allow audio signals below 20kHz to pass through but highly attenuate the high frequency signal content Figure 2 5 Configuration for Using Headphone Amplifier in Class D Mode For using the headphones in the Class D mode of operation the headphones should first be powered up in default Class AB mode to charge the AC coupling capa...

Page 21: ...n In addition to the standard set of stereo decimation filter features the TLV320DAC3203 also offers the following special functions Channel to channel phase adjustment Adaptive filter mode 2 3 1 Digital Microphone Interface The TLV320DAC3203 digital microphone interface is shown in Figure 2 6 Figure 2 6 Digital Microphone in TLV320DAC3203 The TLV320DAC3203 outputs internal clock DIG_MIC_CLK on GP...

Page 22: ... ADC channel this volume control soft steps down to 12 0dB before powering down Due to the soft stepping control soon after changing the volume control setting or powering down the ADC channel the actual applied gain may be different from the one programmed through the control register The TLV320DAC3203 gives feedback to the user through read only flags Page 1 Reg 36 D 7 for Left Channel and Page ...

Page 23: ... FIR filters have fully user programmable coefficients The Resource Class Column RC gives an approximate indication of power consumption Table 2 5 Processing Blocks Processing Channel Decimation 1st Order Number FIR Required Resource Blocks Filter IIR BiQuads AOSR Value Class Available PRB_R1 1 Stereo A Yes 0 No 128 64 6 PRB_R2 Stereo A Yes 5 No 128 64 8 PRB_R3 Stereo A Yes 0 25 Tap 128 64 8 PRB_R...

Page 24: ...put Decimation Filter www ti com 2 3 3 1 Signal Processing Details 2 3 3 1 1 Processing Block Descriptions 2 3 3 1 1 1 1st order IIR Filter A Figure 2 8 Signal Chain for PRB_R1 and PRB_R4 2 3 3 1 1 2 5 Biquads 1st order IIR Filter A Figure 2 9 Signal Chain PRB_R2 and PRB_R5 2 3 3 1 1 3 25 Tap FIR 1st order IIR Filter A Figure 2 10 Signal Chain for PRB_R3 and PRB_R6 2 3 3 1 1 4 1st order IIR Filter...

Page 25: ...ww ti com Digital Microphone Input Decimation Filter 2 3 3 1 1 5 3 Biquads 1st order IIR Filter B Figure 2 12 Signal Chain for PRB_R8 and PRB_R11 2 3 3 1 1 6 20 Tap FIR 1st order IIR Filter B Figure 2 13 Signal Chain for PRB_R9 and PRB_R12 2 3 3 1 1 7 1st order IIR Filter C Figure 2 14 Signal Chain for PRB_R13 and PRB_R16 2 3 3 1 1 8 5 Biquads 1st order IIR Filter C Figure 2 15 Signal Chain for PR...

Page 26: ...rom CIC Filter Digital Microphone Input Decimation Filter www ti com 2 3 3 1 1 9 25 Tap FIR 1st order IIR Filter C Figure 2 16 Signal for PRB_R15 and PRB_R18 26 TLV320DAC3203 Application SLAU434 May 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Page 27: ...ng see Section 2 3 3 2 3 below The coefficients of these filters are each 24 bits wide in two s complement and occupy 3 consecutive 8 bit registers in the register space For default values please see Section 5 17 2 3 3 1 2 1 1st Order IIR Section The transfer function for the first order IIR Filter is given by 2 The frequency response for the 1st order IIR Section with default coefficients is flat...

Page 28: ... Pg 8 Reg 64 65 66 C46 Pg 9 Reg 72 73 74 D1 C15 Pg 8 Reg 68 69 70 C47 Pg 9 Reg 76 77 78 D2 C16 Pg 8 Reg 72 73 74 C48 Pg 9 Reg 80 81 82 BIQUAD C N0 C17 Pg 8 Reg 76 77 78 C49 Pg 9 Reg 84 85 86 N1 C18 Pg 8 Reg 80 81 82 C50 Pg 9 Reg 88 89 90 N2 C19 Pg 8 Reg 84 85 86 C51 Pg 9 Reg 92 93 94 D1 C20 Pg 8 Reg 88 89 90 C52 Pg 9 Reg 96 97 98 D2 C21 Pg 8 Reg 92 93 94 C53 Pg 9 Reg 100 101 102 BIQUAD D N0 C22 Pg...

Page 29: ...3 Pg 9 Reg 60 61 62 Fir5 C12 Pg 8 Reg 56 57 58 C44 Pg 9 Reg 64 65 66 Fir6 C13 Pg 8 Reg 60 61 62 C45 Pg 9 Reg 68 69 70 Fir7 C14 Pg 8 Reg 64 65 66 C46 Pg 9 Reg 72 73 74 Fir8 C15 Pg 8 Reg 68 69 70 C47 Pg 9 Reg 76 77 78 Fir9 C16 Pg 8 Reg 72 73 74 C48 Pg 9 Reg 80 81 82 Fir10 C17 Pg 8 Reg 76 77 78 C49 Pg 9 Reg 84 85 86 Fir11 C18 Pg 8 Reg 80 81 82 C50 Pg 9 Reg 88 89 90 Fir12 C19 Pg 8 Reg 84 85 86 C51 Pg ...

Page 30: ...tes up to 48kHz When configuring this filter the oversampling ratio of the can either be 128 or 64 For highest performance the oversampling ratio must be set to 128 Please also see the PowerTune chapter for details on performance and power in dependency of AOSR Filter A can also be used for 96kHz at an AOSR of 64 Table 2 9 Decimation Filter A Specification Parameter Condition Value Typical Units A...

Page 31: ... ratio of 64 Table 2 10 Decimation Filter B Specifications Parameter Condition Value Typical Units AOSR 64 Filter Gain Pass Band 0 0 39Fs 0 077 dB Filter Gain Stop Band 0 60Fs 32Fs 46 dB Filter Group Delay 11 Fs Sec Pass Band Ripple 8 ksps 0 0 39Fs 0 076 dB Pass Band Ripple 44 1 ksps 0 0 39Fs 0 06 dB Pass Band Ripple 48 ksps 0 0 39Fs 0 06 dB Pass Band Ripple 96 ksps 0 20kHz 0 11 dB Figure 2 18 Dec...

Page 32: ...Group Delay 11 Fs Sec Pass Band Ripple 8 ksps 0 0 11Fs 0 033 dB Pass Band Ripple 44 1 ksps 0 0 11Fs 0 033 dB Pass Band Ripple 48 ksps 0 0 11Fs 0 032 dB Pass Band Ripple 96 ksps 0 0 11Fs 0 032 dB Pass Band Ripple 192 ksps 0 20kHz 0 086 dB Figure 2 19 Decimation Filter C Frequency Response 2 3 3 1 4 ADC Data Interface The decimation filter and signal processing block in the ADC channel passes 32 bit...

Page 33: ... the bias amplifier can work of either a low analog supply or high LDOIN supply Table 2 12 MICBIAS Voltage Control Page 1 Reg 51 D 5 4 Page 1 Reg 10 D 6 Page 1 Reg 51 D 3 MICBIAS Voltage without load 00 0 X 1 25V 00 1 X 1 0V 01 0 X 1 7V 01 1 X 1 4V 10 0 1 2 5V 10 1 1 2 1V 11 X 0 AVdd 11 X 1 LDOIN 2 3 3 2 2 Channel to Channel Phase Adjustment The TLV320DAC3203 has a built in feature to fine adjust ...

Page 34: ...ing discussion is intended to guide a system designer through the steps necessary to configure the TLV320DAC3203 ADC Step 1 The system clock source master clock and the targeted ADC sampling frequency must be identified The oversampling ratio OSR of the TLV320DAC3203 must be configured to match the properties of the digital microphone Based on the identified filter type and the required signal pro...

Page 35: ... delta sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz To handle multiple input rates and optimize performance the TLV320DAC3203 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input d...

Page 36: ...s 6 Yes No No 12 PRB_P3 A Stereo Yes 6 No No No 10 PRB_P4 A Left No 3 No No No 4 PRB_P5 A Left Yes 6 Yes No No 6 PRB_P6 A Left Yes 6 No No No 6 PRB_P7 B Stereo Yes 0 No No No 6 PRB_P8 B Stereo No 4 Yes No No 8 PRB_P9 B Stereo No 4 No No No 8 PRB_P10 B Stereo Yes 6 Yes No No 10 PRB_P11 B Stereo Yes 6 No No No 8 PRB_P12 B Left Yes 0 No No No 3 PRB_P13 B Left No 4 Yes No No 4 PRB_P14 B Left No 4 No N...

Page 37: ...ital Volume Ctrl from Interface www ti com DAC 2 4 1 2 6 Biquads 1st order IIR DRC Interpolation Filter A or B Figure 2 21 Signal Chain for PRB_P2 PRB_P5 PRB_P10 and PRB_P15 2 4 1 3 6 Biquads 1st order IIR Interpolation Filter A or B Figure 2 22 Signal Chain for PRB_P3 PRB_P6 PRB_P11 and PRB_P16 2 4 1 4 IIR Interpolation Filter B or C Figure 2 23 Signal Chain for PRB_P7 PRB_P12 PRB_P17 and PRB_P20...

Page 38: ...Filter C DRC HPF IIR to Modulator Digital Volume Ctrl BiQuad D BiQuad C BiQuad B BiQuad A from Interface DAC www ti com 2 4 1 7 4 Biquads 1st order IIR DRC Interpolation Filter B Figure 2 26 Signal Chain for PRB_P18 and PRB_P21 2 4 1 8 4 Biquads 1st order IIR Interpolation Filter C Figure 2 27 Signal Chain for PRB_P19 and PRB_P22 2 4 1 9 2 Biquads 3D Interpolation Filter A Figure 2 28 Signal Chain...

Page 39: ...CR BiQuad BR IIR Right from Left Channel Interface to Modulator to Modulator Digital Volume Ctrl Digital Volume Ctrl from Right Channel Interface BiQuad BL BiQuad CL BiQuad DL www ti com DAC 2 4 1 10 5 Biquads DRC 3D Interpolation Filter A Figure 2 29 Signal Chain for PRB_P24 2 4 1 11 5 Biquads DRC 3D Beep Generator Interpolation Filter A Figure 2 30 Signal Chain for PRB_P25 2 4 2 User Programmabl...

Page 40: ... frequency response for each biquad section with default coefficients is flat at a gain of 0dB Details on DAC coefficient default values are given in Section 5 19 Table 2 15 DAC Biquad Filter Coefficients Filter Coefficient Left DAC Channel Right DAC Channel BIQUAD A N0 C1 Page 44 Registers 12 13 14 C33 Page 45 Registers 20 21 22 N1 C2 Page 44 Registers 16 17 18 C34 Page 45 Registers 24 25 26 N2 C...

Page 41: ...s 112 113 114 D2 C25 Page 44 Registers 108 109 110 C57 Page 45 Registers 116 117 118 BIQUAD F N0 C26 Page 44 Registers 112 113 114 C58 Page 45 Registers 120 121 122 N1 C27 Page 44 Registers 116 117 118 C59 Page 45 Registers 124 125 126 N2 C28 Page 44 Registers 120 121 122 C60 Page 46 Registers 8 9 10 D1 C29 Page 44 Registers 124 125 126 C61 Page 46 Registers 12 13 14 D2 C30 Page 45 Registers 8 9 1...

Page 42: ...0 45Fs 0 015 dB Filter Gain Stop Band 0 55Fs 7 455Fs 65 dB Filter Group Delay 21 Fs s Figure 2 31 DAC Interpolation Filter A Frequency Response 2 4 3 2 Interpolation Filter B Filter B is specifically designed for an Fs of above 96ksps Thus the flat pass band region easily covers the required audio band of 0 20kHz Table 2 17 DAC Interpolation Filter B Specification Parameter Condition Value Typical...

Page 43: ...ation Filter B Frequency Response 2 4 3 3 Interpolation Filter C Filter C is specifically designed for the 192ksps mode The pass band extends up to 0 40 Fs corresponds to 80kHz more than sufficient for audio applications Figure 2 33 DAC Interpolation Filter C Frequency Response Table 2 18 DAC Interpolation Filter C Specification Parameter Condition Value Typical Units Filter Gain Pass Band 0 0 35F...

Page 44: ...ping of peak signals the gain of the DAC channel must be adjusted so as not to cause hard clipping of peak signals As a result during nominal periods the applied gain is low causing the perception that the signal is not loud enough To overcome this problem the DRC in the TLV320DAC3203 continuously monitors the output of the DAC Digital Volume control to detect its power level w r t 0dB FS When the...

Page 45: ...Bits D3 D2 are updated These flag bits are sticky in nature and are reset only after they are read back by the user The non sticky versions of the interrupt flags are also available at Page 0 Register 46 Bits D3 D2 2 4 4 2 2 DRC Hysteresis DRC Hysteresis is programmable by writing to Page 0 Register 68 Bits D1 D0 It can be programmed to values between 0dB and 3dB in steps of 1dB It is a programmab...

Page 46: ...ol is gradually increased to programmed values To avoid audible artifacts the gain is slowly increased with a rate equal to the Decay Rate programmed through Page 0 Register 70 Bits D3 D0 The Decay Rates can be programmed from 1 5625e 3dB per 1 DAC_FS to 4 7683e 7dB per 1 DAC_FS If the Decay Rates are programmed too high then sudden gain changes can cause audible artifacts However if it is program...

Page 47: ...sine wave gets started by setting the Beep Generator Enable Bit Page 1 Register 71 Bit D7 1 After the sine wave has played for its predefined time period this bit will automatically set back to 0 While the sine wave is playing the parameters of the beep generator cannot be changed To stop the sine wave while it is playing set the Beep Generator Enable Bit to 0 2 4 5 2 Digital Auto Mute The TLV320D...

Page 48: ...termined from the list of available processing blocks PRB_P1 to PRB_P25 Based on the available master clock the chosen DOSR and the targeted sampling rate the clock divider values NDAC and MDAC can be determined If necessary the internal PLL can add a large degree of flexibility In summary Codec_Clkin derived directly from the system clock source or from the internal PLL divided by MDAC NDAC and D...

Page 49: ...r Apply waiting time determined by the de pop settings and the soft stepping settings of the driver gain or poll Page 1 Register 63 Power Up DAC Set register Page to 0 Power up DAC Channels Unmute digital volume control 2 5 PowerTune The TLV320DAC3203 features PowerTune a mechanism to balance power versus performance trade offs at the time of device configuration The device can be tuned to minimiz...

Page 50: ...or recording also influences the power consumption In fact the numerous processing blocks have been implemented to offer a choice between power optimization and configurations with more signal processing resources 50 TLV320DAC3203 Application SLAU434 May 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Page 51: ...dB full scale 1 75 211 375 375 100 281 500 500 mVRMS HP out Effective SNR w r t 88 4 93 4 97 0 96 7 90 7 95 3 99 2 100 1 dB 32Ω 0dB full scale load Power 9 7 10 6 11 3 11 3 9 7 10 6 11 3 11 3 mW consumption 2 Power 8 1 9 0 9 7 9 7 8 1 9 0 9 7 9 7 mW consumption 3 1 Reduced 0dB full scale swing can be compensated by applying appropriate gain in the output drivers see 2 Measured data using PRB_P8 3 ...

Page 52: ...alculated data for PRB_P7 Alternative processing blocks Processing Block Filter Est Power Change mW 1 PRB_P1 A 0 PRB_P2 A 1 5 PRB_P3 A 0 8 PRB_P7 B 0 8 PRB_P9 B 0 PRB_P10 B 0 8 PRB_P11 B 0 PRB_P23 A 0 PRB_P24 A 1 5 PRB_P25 A 1 5 1 Estimated power change is w r t PRB_P8 2 5 2 3 DAC Mono 48kHz Highest Performance DVdd 1 8V AVdd 1 8V DOSR 128 Processing Block PRB_P13 Interpolation Filter B Device Com...

Page 53: ...Filter Est Power Change mW PRB_P4 A 0 PRB_P5 A 0 8 PRB_P6 A 0 8 PRB_P12 B 0 4 PRB_P14 B 0 PRB_P15 B 0 8 PRB_P16 B 0 2 5 2 5 DAC Stereo 8kHz Highest Performance DVdd 1 8V AVdd 1 8V DOSR 768 Processing Block PRB_P7 Interpolation Filter B Device Common Mode Setting 0 75V Device Common Mode Setting 0 9V PTM_P1 PTM_P2 PTM_P3 PTM_P4 PTM_P1 PTM_P2 PTM_P3 PTM_P4 UNIT 0dB full scale 75 211 375 375 100 281 ...

Page 54: ... PRB_P8 B 0 1 PRB_P9 B 0 1 PRB_P10 B 0 3 PRB_P11 B 0 1 PRB_P23 A 0 1 PRB_P24 A 0 4 PRB_P25 A 0 4 2 5 2 7 DAC Mono 8kHz Highest Performance DVdd 1 8V AVdd 1 8V DOSR 768 Processing Block PRB_P4 Interpolation Filter A Device Common Mode Setting 0 75V Device Common Mode Setting 0 9V PTM_P1 PTM_P2 PTM_P3 PTM_P4 PTM_P1 PTM_P2 PTM_P3 PTM_P4 UNIT 0dB full scale 1 75 211 375 375 100 281 500 500 mVRMS HP ou...

Page 55: ..._P12 B 0 1 PRB_P13 B 0 PRB_P14 B 0 PRB_P15 B 0 1 PRB_P16 B 0 2 5 2 9 DAC Stereo 192kHz DVdd 1 8V AVdd 1 8V DOSR 32 Processing Block PRB_P17 Interpolation Filter C Device Common Mode Setting 0 75V Device Common Mode Setting 0 9V PTM_P1 PTM_P2 PTM_P3 PTM_P4 PTM_P1 PTM_P2 PTM_P3 PTM_P4 UNIT 0dB full scale 1 75 211 375 375 100 281 500 500 mVRMS HP out Effective SNR w r t 88 3 92 1 96 4 97 2 90 7 94 6 ...

Page 56: ...and may be programmed as either a pulse or a square wave signal The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies The bit clock is used to clock in and clock out the digital audio data across the serial bus When in Master mode this signal can be programmed to generate variable clock pulses by controlling the bit clock divider in Page 0 Register...

Page 57: ...or bit clocks are used in the system as general purpose clocks 2 6 1 Right Justified Mode The Audio Interface of the TLV320DAC3203 can be put into Right Justified Mode by programming Page 0 Register 27 D 7 6 10 In right justified mode the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock Similarly the LSB of the right channel is valid...

Page 58: ...Left Justified Mode by programming Page 0 Register 27 D 7 6 11 In left justified mode the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock Figure 2 35 Timing Diagram for Left Justified Mode Figure 2 36 Timin...

Page 59: ...e put into I2 S Mode by programming Page 0 Register 27 D 7 6 to 00 In I2 S mode the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock Figure 2 38 Timing Diagram for I2 S Mode Figure 2 39 Timing Diagram ...

Page 60: ...e put into DSP Mode by programming Page 0 Register 27 D 7 6 01 In DSP mode the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data Each data bit is valid on the falling edge of the bit clock Figure 2 41 Timing Diagram for DSP Mode Figure 2 42 Timing Diagram for DSP Mode with offset 1 Figure 2 43 Timing Diagram f...

Page 61: ...s an extensive IO control to allow communication with two independent processors for audio data Each processor can communicate with the device one at a time This feature is enabled by register programming of the various pin selections Figure 2 44 Audio Serial Interface Multiplexing The secondary audio interface uses multifunction pins For an overview on multifunction pins please see Section 2 1 3 ...

Page 62: ...cks for the DAC require a source reference clock This clock can be provided on a variety of device pins such as MCLK BCLK or GPIO pins The CODEC_CLKIN can then be routed through highly flexible clock dividers to generate the various clocks required for the DAC sections In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK BCLK or GPIO the TLV320DAC3203 al...

Page 63: ...8 D 7 1 and Page 0 Register 19 D 7 1 When the ADC channel is powered down the device internally initiates a power down sequence for proper shut down During this shut down sequence the NADC and MADC dividers must not be powered down or else a proper low power shut down may not take place The user can read the power status flag in Page 0 Register 36 D 6 and Page 0 Register 36 D 2 When both flags ind...

Page 64: ...om 1 to 128 by writing to Page 0 Register 26 D 6 0 The CDIV_CLKIN can itself be programmed as one of the clocks among the list shown in Figure 2 47 This can be controlled by programming the mux in Page 0 Register 25 D 2 0 Figure 2 47 General Purpose Clock Output Options Table 2 21 Maximum TLV320DAC3203 Clock Frequencies DVdd 1 26V DVdd 1 65V CODEC_CLKIN 50MHz 137MHz when NDAC is even NADC is even ...

Page 65: ...Page 0 Register 6 D 5 0 The variable D is 12 bits programmed into two registers The MSB portion can be programmed via Page 0 Register 7 D 5 0 and the LSB portion is programmed via Page 0 Register 8 D 7 0 The default register value for D is 0 When the PLL is enabled the following conditions must be satisfied When the PLL is enabled and D 0 the following conditions must be satisfied for PLL_CLKIN 18...

Page 66: ...2 C communication protocols with the protocol selectable using the SPI_SELECT pin For SPI SPI_SELECT should be tied high for I2 C SPI_SELECT should be tied low It is not recommended to change the state of SPI_SELECT during device operation 2 8 1 I2 C Control Mode The TLV320DAC3203 supports the I2 C control protocol and will respond to the I2 C address of 0011000 I2 C is a two wire open drain inter...

Page 67: ...ddress byte Each device on an I2 C bus has a unique 7 bit address to which it responds Slaves can also have 10 bit addresses see the I2 C specification for details The master sends an address in the address byte together with a bit that indicates whether it wishes to read from or write to the slave device Every byte transmitted on the I2 C bus whether it is address or data is acknowledged with an ...

Page 68: ...e TLV320DAC3203 interface is designed so that with a clock phase bit setting of 1 typical microprocessor SPI control bit CPHA 1 the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge The SSZ pin can remain low between transmissions however the TLV320DAC3203 only interprets the first 8 bits transmitted after the falling edge of SSZ as a comma...

Page 69: ...et to 0 75V Pg 1 Reg 10 D 6 1 resulting in 375mVrms internal full scale voltage NOTE At powerup AVdd is weakly connected to DVdd This coarse AVdd generation must be turned off by writing Pg 1 Reg 1 D 3 1 at the time AVdd is applied either from internal LDO or through external LDO LDOin The LDOin pin serves two main functions It serves as supply to the internal LDO as well as to the analog output a...

Page 70: ... to power the device Apply the following rules During normal operation all supply pins must be connected to a supply via internal LDO or external Whenever the LDOin supply is present DVdd supply must be present as well If AVdd supply is not present then the crude internal AVdd generation must be turned on Pg 1 Reg 1 D 3 0 Whenever the DVdd supply is on and either AVdd or LDOin or both supplies are...

Page 71: ... in headphones Data Overflow in ADC and DAC Processing Blocks and Filters Each of these INT1 and INT2 interrupts can be routed to output pins like GPIO DOUT and MISO by configuring the respective output control registers in Page 0 Register 52 53 and 55 These interrupt signals can either be configured as a single pulse or a series of pulses by programming Page 0 Register 48 D 0 and Page 0 Register ...

Page 72: ...ecial functions that may add value to the end application Example device setups are described in the final section Topic Page 3 1 Reset 73 3 2 Device Startup Lockout Times 73 3 3 Analog and Reference Startup 73 3 4 PLL Startup 73 3 5 Setting Device Common Mode Voltage 73 72 Device Initialization SLAU434 May 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Page 73: ...the Analog Reference block must be powered up By default the Analog Reference block will implicitly be powered up whenever any analog block is powered up or it can be powered up independently Detailed descriptions of Analog Reference including fast power up options are provided in During the time that the reference block is not completely powered up subsequent requests for powering up analog block...

Page 74: ... w 30 00 01 Disable internal crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO w 30 01 08 Enable master analog power control w 30 02 00 Set the REF charging time to 40ms w 30 7b 01 Set the input common mode to 0 9V and output common mode for headphone to input common mode w 30 0a 00 Route left DAC to HPL w 30 0c 08 Route right DAC to HPR w 30 0d 08 Set the DAC ...

Page 75: ... REF charging time to 40ms w 30 7b 01 Set the input common mode to 0 9V and output common mode for headphone to input common mode w 30 0a 00 Route left DAC to HPL w 30 0c 08 Route right DAC to HPR w 30 0d 08 Set the DAC PTM mode to PTM_P1 w 30 03 08 w 30 04 08 Set the HPL gain to 0dB w 30 10 00 Set the HPR gain to 0dB w 30 11 00 HP soft stepping settings for optimal pop performance at power up Rpo...

Page 76: ...ble class D mode for HPR output w 30 04 c0 Route left DAC to HPL w 30 0c 08 Route right DAC to HPR w 30 0d 08 Unmute HPL driver w 30 10 00 Unmute HPR driver w 30 11 00 HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N 6 soft step 20usec w 30 14 29 Power up HPL and HPR drivers w 30 09 30 Wait for 2 5 sec for soft stepping to take effect Else read Page 1 Regist...

Page 77: ...AVdd supply or before powering up internal AVdd LDO w 30 01 08 Enable master analog power control w 30 02 00 Set the REF charging time to 40ms w 30 7b 01 Select page 0 w 30 00 00 Select PRB_R2 w 30 3d 02 Configure MISO as clock output for digital microphone w 30 37 0e Power up left ADC and right ADC Enable digital microphone mode for left ADC and right ADC Treat data on SCLK as digital microphone ...

Page 78: ...B w 30 10 05 Unmute HPR gain set to 5dB w 30 11 05 Offset calibration mode 01 w 30 7d 01 Device common mode 0 75V heaephone output common mode 1 5V Headphone powered by LDOIN supply and LDONIN 1 8V w 30 0a 63 Select page 0 w 30 00 00 Select PRB_P1 for DAC playback w 30 3c 01 Power up left DAC w 30 3f 94 Select page 1 w 30 00 01 Power up HPL and HPR w 30 09 30 Poll page 1 register 2 D2 If the bit i...

Page 79: ... filtering control and DAC Coefficient Buffer A 0 29 See Table 5 5 45 46 DAC Coefficient BufferA 30 76 See Table 5 5 and Table 5 7 47 61 Reserved 62 64 DAC Coefficient BufferB C 0 76 See Table 5 6 and Table 5 7 65 255 Reserved 5 2 Page 0 Registers 5 2 1 Page 0 Register 0 Page Select Register 0x00 0x00 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W 0000 0000 Page Select Register 0 255 Selects the...

Page 80: ... Package 11 PLL Clock is CODEC_CLKIN 5 2 6 Page 0 Register 5 Clock Setting Register 2 PLL P R Values 0x00 0x05 READ RESET BIT DESCRIPTION WRITE VALUE D7 R W 0 PLL Power Up 0 PLL is powered down 1 PLL is powered up D6 D4 R W 001 PLL divider P Value 000 P 8 001 P 1 010 P 2 110 P 6 111 P 7 D3 D0 R W 0001 PLL divider R Value 000 Reserved do not use 001 R 1 010 R 2 011 R 3 100 R 4 101 111 Reserved do n...

Page 81: ...en immediately after Page 0 Reg 7 5 2 10 Page 0 Register 9 10 Reserved Register 0x00 0x09 0x0A READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 2 11 Page 0 Register 11 Clock Setting Register 6 NDAC Values 0x00 0x0B READ RESET BIT DESCRIPTION WRITE VALUE D7 R W 0 NDAC Divider Power Control 0 NDAC divider powered down 1 NDAC divider powered up D6 D0 R W 0...

Page 82: ... 11 1111 1110 DOSR 1022 11 1111 1111 Reserved Do not use Note This register should be written immediately after Page 0 Reg 13 Note DOSR should be a multiple of 2 while using DAC Filter Type A Multiple of 4 while using DAC Filter Type B and Multiple of 8 while using DAC Filter Type C 5 2 15 Page 0 Register 15 Reserved Register 0x00 0x0F READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0010 Reser...

Page 83: ...0000 0100 Reserved Write only default values 5 2 24 Page 0 Register 24 Reserved Register 0x00 0x18 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 2 25 Page 0 Register 25 Clock Setting Register 8 Multiplexers 0x00 0x19 READ RESET BIT DESCRIPTION WRITE VALUE D7 D3 R 0000 0 Reserved Write only default values D2 D0 R W 000 CDIV_CLKIN Clock Selection 000 C...

Page 84: ...et 0 BCLK s 0000 0001 Data Offset 1 BCLK s 1111 1110 Data Offset 254 BCLK s 1111 1111 Data Offset 255 BCLK s 5 2 29 Page 0 Register 29 Audio Interface Setting Register 3 0x00 0x1D READ RESET BIT DESCRIPTION WRITE VALUE D7 D6 R W 00 Reserved Write only default values D5 R W 0 Loopback control 0 No Loopback 1 Audio Data in is routed to Audio Data out DOUT signal on MFP2 D4 R W 0 Reserved Write only ...

Page 85: ... R W 0 Secondary Data Input Multiplexer 0 Secondary Data Input GPIO Availble only for WCSP Package 1 Secondary Data Input SCLK 5 2 32 Page 0 Register 32 Audio Interface Setting Register 5 0x00 0x20 READ RESET BIT DESCRIPTION WRITE VALUE D7 D4 R 0000 Reserved Write only default values D3 R W 0 Primary Secondary Bit Clock Control 0 Primary Bit Clock BCLK is used for Audio Interface and Clocking 1 Se...

Page 86: ... default value D5 R W 0 I2C General Call Address Configuration 0 I2C General Call Address will be ignored 1 I2C General Call Address accepted D4 D0 R 0 0000 Reserved Write only default values 5 2 35 Page 0 Register 35 36 Reserved Register 0x00 0x23 0x24 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default value 5 2 36 Page 0 Register 37 DAC Flag Register 1 0x00 0x25...

Page 87: ... 0x00 0x2B READ RESET BIT DESCRIPTION WRITE VALUE D7 R 0 Left DAC Overflow Status 0 No overflow in Left DAC 1 Overflow condition is present in Left ADC at the time of reading the register D6 R 0 Right DAC Overflow Status 0 No overflow in Right DAC 1 Overflow condition is present in Right DAC at the time of reading the register D5 D4 R 00 Reserved D3 R 0 Left ADC Overflow Status 0 No overflow in Le...

Page 88: ... R 0 Left Channel DRC Signal Threshold Flag 0 Signal Power is below Signal Threshold 1 Signal Power exceeded Signal Threshold D2 R 0 Right Channel DRC Signal Threshold Flag 0 Signal Power is below Signal Threshold 1 Signal Power exceeded Signal Threshold D1 D0 R 00 Reserved 5 2 44 Page 0 Register 47 Reserved Register 0x00 0x2F READ RESET BIT DESCRIPTION WRITE VALUE D7 D5 R 0000 0000 Reserved Write...

Page 89: ...5 R W 0 INT2 Interrupt for DAC DRC Signal Threshold 0 DAC DRC Signal Power exceeding Signal Threshold will not generate a INT2 interrupt 1 DAC DRC Signal Power exceeding Signal Threshold for either of Left or Right Channel will generate a INT2 interrupt Read Page 0 Register 44 to distinguish between Left or Right Channel D4 R 0 Reserved Write only default value D3 R W 0 INT2 Interrupt for Over Cur...

Page 90: ... Control Register 0x00 0x35 READ RESET BIT DESCRIPTION WRITE VALUE D7 D5 R 000 Reserved Write only default values D4 R W 1 MFP2 Bus Keeper Control 0 MFP2 Bus Keeper Enabled 1 MFP2 Bus Keeper Disabled D3 D1 R W 001 MFP2 MUX Control 000 MFP2 disabled 001 MFP2 is Primary DOUT Loopback data 010 MFP2 is General Purpose Output 011 MFP2 is CLKOUT 100 MFP2 is INT1 101 MFP2 is INT2 110 MFP2 is Secondary BC...

Page 91: ...condary Data Input or Secondary Bit Clock Input or Secondary Word Clock or Digital Microphone Input 10 SCLK is enabled as General Purpose Input 11 Reserved Do not use D0 R X Value of SCLK input pin when used as General Purpose Input 5 2 53 Page 0 Register 57 59 Reserved Registers 0x00 0x39 0x3B READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 2 54 Page ...

Page 92: ...ight Channel Audio Interface Data 10 Right DAC data is Left Channel Audio Interface Data 11 Right DAC data is Mono Mix of Left and Right Channel Audio Interface Data D1 D0 R W 00 DAC Channel Volume Control s Soft Step control 00 Soft Stepping is 1 step per 1 DAC Word Clock 01 Soft Stepping is 1 step per 2 DAC Word Clocks 10 Soft Stepping is disabled 11 Reserved Do not use 5 2 58 Page 0 Register 64...

Page 93: ...d Do not use 5 2 60 Page 0 Register 66 Right DAC Channel Digital Volume Control Register 0x00 0x42 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W 0000 0000 Right DAC Channel Digital Volume Control Setting 0111 1111 0011 0001 Reserved Do not use 0011 0000 Digital Volume Control 24dB 0010 1111 Digital Volume Control 23 5dB 0000 0001 Digital Volume Control 0 5dB 0000 0000 Digital Volume Control 0 0...

Page 94: ...00 DRC Hysteresis 0dB 01 DRC Hysteresis 1dB 10 DRC Hysteresis 2dB 11 DRC Hysteresis 3dB 5 2 63 Page 0 Register 69 DRC Control Register 2 0x00 0x45 READ RESET BIT DESCRIPTION WRITE VALUE D7 R 0 Reserved Write only default value D6 D3 R W 0111 DRC Hold Programmability 0000 DRC Hold Disabled 0001 DRC Hold Time 32 DAC Word Clocks 0010 DRC Hold Time 64 DAC Word Clocks 0011 DRC Hold Time 128 DAC Word Cl...

Page 95: ...00 0x48 READ RESET BIT DESCRIPTION WRITE VALUE D7 D6 R W 00 Beep Generator Master Volume Control Setting 00 Left and Right Channels have independent Volume Settings 01 Left Channel Beep Volume is the same as programmed for Right Channel 10 Right Channel Beep Volume is the same as programmed for Left Channel 11 Reserved Do not use D5 D0 R 00 0000 Right Channel Beep Volume Control 00 0000 Right Chan...

Page 96: ...Reserved Register 0x00 0x50 READ RESET BIT DESCRIPTION WRITE VALUE x 0 81 Reserved Register D7 R W 0 Left Channel ADC Power Control 0 Left Channel ADC is powered down 1 Left Channel ADC is powered up D6 R W 0 Right Channel ADC Power Control 0 Right Channel ADC is powered down 1 Right Channel ADC is powered up D5 D4 R W 00 Digital Microphone Input Configuration 00 GPIO serves as Digital Microphone ...

Page 97: ...eft ADC Channel Volume Control 000 0000 110 0111 Reserved Do not use 110 1000 Left ADC Channel Volume 12dB 110 1001 Left ADC Channel Volume 11 5dB 110 1010 Left ADC Channel Volume 11 0dB 111 1111 Left ADC Channel Volume 0 5dB 000 0000 Left ADC Channel Volume 0 0dB 000 0001 Left ADC Channel Volume 0 5dB 010 0110 Left ADC Channel Volume 19 0dB 010 0111 Left ADC Channel Volume 19 5dB 010 1000 Left AD...

Page 98: ...ite command Refer Table Summary of Memory Map for details 5 3 2 Page 1 Register 1 Power Configuration Register 0x01 0x01 READ RESET BIT DESCRIPTION WRITE VALUE D7 D4 R 0000 Reserved Write only default values D3 R W 0 0 AVDD will be weakly connected to DVDD Use when DVDD is powered but AVDD LDO is powered down and AVDD is not externally powered 1 Disabled weak connection of AVDD with DVDD D2 D0 R 0...

Page 99: ...05 0x08 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 3 7 Page 1 Register 9 Output Driver Power Control Register 0x01 0x09 READ RESET BIT DESCRIPTION WRITE VALUE D7 D6 R 00 Reserved Write only default value D5 R W 0 0 HPL is powered down 1 HPL is powered up D4 R W 0 0 HPR is powered down 1 HPR is powered up D3 D0 R 000 Reserved Write only default val...

Page 100: ...al is not routed to HPL 1 Left Channel DAC reconstruction filter s positive terminal is routed to HPL D2 R W 0 0 IN1L is not routed to HPL 1 IN1L is routed to HPL D1 D0 R W 00 Reserved Write only default values 5 3 11 Page 1 Register 13 HPR Routing Selection Register 0x01 0x0D READ RESET BIT DESCRIPTION WRITE VALUE D7 D5 R 000 Reserved Write only default values D4 R W 0 0 Left Channel DAC reconstr...

Page 101: ...is muted D5 D0 R W 00 0000 10 0000 11 1001 Reserved Do not use 11 1010 HPR driver gain is 6dB Note It is not possible to mute HPR while programmed to 6dB 11 1011 HPR driver gain is 5dB 11 1100 HPR driver gain is 4dB 00 0000 HPR driver gain is 0dB 01 1011 HPR driver gain is 27dB 01 1100 HPR driver gain is 28dB 01 1101 HPR driver gain is 29dB 01 1110 01 1111 Reserved Do not use Note These gains are ...

Page 102: ... up slowly in 7 0 time constants 1100 Headphone amps power up slowly in 8 0 time constants 1101 Headphone amps power up slowly in 16 0 time constants do not use for Rchg 25K 1110 Headphone amps power up slowly in 24 0 time constants do not use for Rchg 25K 1111 Headphone amps power up slowly in 32 0 time constants do not use for Rchg 25K Note Time constants assume 47uF decoupling cap D1 D0 R W 00 ...

Page 103: ...Volume Control 15 5dB 001 1110 Volume Control 16 0dB 001 1111 Volume Control 16 5dB 010 0000 Volume Control 17 1dB 010 0001 Volume Control 17 5dB 010 0010 Volume Control 18 1dB 010 0011 Volume Control 18 6dB 010 0100 Volume Control 19 1dB 010 0101 Volume Control 19 6dB 010 0110 Volume Control 20 1dB 010 0111 Volume Control 20 6dB 010 1000 Volume Control 21 1dB 010 1001 Volume Control 21 6dB 010 10...

Page 104: ...46 2dB 101 1010 Volume Control 46 7dB 101 1011 Volume Control 47 4dB 101 1100 Volume Control 47 9dB 101 1101 Volume Control 48 2dB 101 1110 Volume Control 48 7dB 101 1111 Volume Control 49 3dB 110 0000 Volume Control 50 0dB 110 0001 Volume Control 50 3dB 110 0010 Volume Control 51 0dB 110 0011 Volume Control 51 42dB 110 0100 Volume Control 51 82dB 110 0101 Volume Control 52 3dB 110 0110 Volume Con...

Page 105: ...Volume Control 15 5dB 001 1110 Volume Control 16 0dB 001 1111 Volume Control 16 5dB 010 0000 Volume Control 17 1dB 010 0001 Volume Control 17 5dB 010 0010 Volume Control 18 1dB 010 0011 Volume Control 18 6dB 010 0100 Volume Control 19 1dB 010 0101 Volume Control 19 6dB 010 0110 Volume Control 20 1dB 010 0111 Volume Control 20 6dB 010 1000 Volume Control 21 1dB 010 1001 Volume Control 21 6dB 010 10...

Page 106: ...1 1101 Volume Control 48 2dB 101 1110 Volume Control 48 7dB 101 1111 Volume Control 49 3dB 110 0000 Volume Control 50 0dB 110 0001 Volume Control 50 3dB 110 0010 Volume Control 51 0dB 110 0011 Volume Control 51 42dB 110 0100 Volume Control 51 82dB 110 0101 Volume Control 52 3dB 110 0110 Volume Control 52 7dB 110 0111 Volume Control 53 7dB 110 1000 Volume Control 54 2dB 110 1001 Volume Control 55 4...

Page 107: ...not routed to HPR D5 D0 R 00 0000 Reserved Write only default value 5 3 24 Page 1 Register 59 62 Reserved Register 0x01 0x3B 0x3E READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 1000 0000 Reserved Write only default values 5 3 25 Page 1 Register 63 DAC Analog Gain Control Flag Register 0x01 0x3F READ RESET BIT DESCRIPTION WRITE VALUE D7 R 0 HPL Gain Flag 0 Applied Gain is not equal to Programmed Ga...

Page 108: ...ence Power up time will be 80ms 111 Force power up of reference Power up time will be 120ms 5 3 30 Page 1 Register 124 Reserved Register 0x01 0x7C READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 3 31 Page 1 Register 125 Offset Callibration Register 0x01 0x7D READ RESET BIT DESCRIPTION WRITE VALUE D7 D5 R 000 Offset correction Clock Divider 000 Offset c...

Page 109: ... ADC Coefficient Buffers will be switched at next frame boundary if in adaptive filtering mode This will self clear on switching 5 4 3 Page 8 Register 2 7 Reserved 0x08 0x02 0x07 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 4 4 Page 8 Register 8 127 ADC Coefficients Buffer A C 0 29 0x08 0x08 0x7F READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W xxxx...

Page 110: ...IT DESCRIPTION WRITE VALUE D7 D0 R W 0000 0000 Page Select Register 0 255 Selects the Register Page for next read or write command Refer Table Summary of Memory Map for details 5 6 2 Page 10 Register 1 7 Reserved 0x0A 0x01 0x07 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 6 3 Page 10 Register 8 23 ADC Coefficients Buffer A C 60 63 0x0A 0x08 0x17 REA...

Page 111: ...1 0x1B 0x08 0x0F READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W xxxx xxxx 24 bit coefficients of ADC Coefficient Buffer B Refer to Table ADC Coefficient Buffer B Map for details When Page 8 Reg 01d D2 0 Adaptive filtering disabled the read write access to these registers is allowed only when ADC channel is powered down 5 8 4 Page 27 Register 16 31 Reserved 0x1B 0x10 0x1F READ RESET BIT DESCRIPTI...

Page 112: ...y default values D2 R W 0 DAC Adaptive Filtering Control 0 Adaptive Filtering disabled for DAC 1 Adaptive Filtering enabled for DAC D1 R 0 DAC Adaptive Filter Buffer Control Flag 0 In adaptive filter mode DAC accesses DAC Coefficient Buffer A and control interface accesses DAC Coefficient Buffer B 1 In adaptive filter mode DAC accesses DAC Coefficient Buffer B and control interface accesses DAC Co...

Page 113: ...2 59 0x2D 0x10 0x7F READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W xxxx xxxx 24 bit coefficients DAC Coefficient Buffer A Refer to Table DAC Coefficient Buffer A Map for details When Page 44 Reg 01d D2 0 Adaptive filtering disabled the read write access to these registers is allowed only when DAC channel is powered down 5 12 Page 46 Registers 5 12 1 Page 46 Register 0 Page Select Register 0x2E 0...

Page 114: ...or write command Refer Table Summary of Memory Map for details 5 13 2 Page 62 Register 1 7 Reserved 0x3E 0x01 0x07 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 13 3 Page 62 Register 8 127 DAC Coefficients Buffer B C 0 29 0x3E 0x08 0x7F READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W xxxx xxxx 24 bit coefficients of DAC Coefficient Buffer B Refer Ta...

Page 115: ...ect Register 0 255 Selects the Register Page for next read or write command Refer Table Summary of Memory Map for details 5 15 2 Page 63 Register 1 7 Reserved 0x3F 0x01 0x07 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R 0000 0000 Reserved Write only default values 5 15 3 Page 63 Register 8 19 DAC Coefficients Buffer B C 60 62 0x3F 0x08 0x13 READ RESET BIT DESCRIPTION WRITE VALUE D7 D0 R W xxxx xx...

Page 116: ...f 7 0 Reserved Table 5 3 ADC Coefficient Buffer B Map Coef No Page No Base Base Register 0 Base Register 1 Base Register 2 Base Register 3 Register C0 26 8 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C1 26 12 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C29 26 124 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C30 27 8 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C59 27 124 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C60 28 8 ...

Page 117: ...ase Register 2 Base Register 3 C0 44 8 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C1 44 12 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C29 44 124 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C30 45 8 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C59 45 124 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C60 46 8 Coef 23 16 Coef 15 8 Coef 7 0 Reserved C76 46 124 Coef 23 16 Coef 15 8 Coef 7 0 Reserved Table 5 6 DAC Coefficient Bu...

Page 118: ...alue at reset C0 00000000H C1 7FFFFF00H C2 C5 00000000H C6 7FFFFF00H C7 C10 00000000H C11 7FFFFF00H C12 C15 00000000H C16 7FFFFF00H C17 C20 00000000H C21 7FFFFF00H C22 C25 00000000H C26 7FFFFF00H C27 C30 00000000H C31 C32 00000000H C33 7FFFFF00H C34 C37 00000000H C38 7FFFFF00H C39 C42 00000000H C43 7FFFFF00H C44 C47 00000000H C48 7FFFFF00H C49 C52 00000000H C53 7FFFFF00H C54 C57 00000000H C58 7FFF...

Page 119: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

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