Page 0 Registers
5.2.27
Page 0 / Register 27: Audio Interface Setting Register 1 - 0x00 / 0x1B
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7-D6
R/W
00
Audio Interface Selection
00: Audio Interface = I2S
01: Audio Interface = DSP
10: Audio Interface = RJF
11: Audio Interface = LJF
D5-D4
R/W
00
Audio Data Word length
00: Data Word length = 16 bits
01: Data Word length = 20 bits
10: Data Word length = 24 bits
11: Data Word length = 32 bits
D3
R/W
0
BCLK Direction Control
0: BCLK is input to the device
1: BCLK is output from the device
D2
R/W
0
WCLK Direction Control
0: WCLK is input to the device
1: WCLK is output from the device
D1
R
0
Reserved. Write only default value
D0
R/W
0
MFP2 (DOUT of loopback data) High Impendance Output Control
0: MFP2 will not be high impedance while Audio Interface is active
1: MFP2 will be high impedance after data has been transferred
5.2.28
Page 0 / Register 28: Audio Interface Setting Register 2, Data offset setting - 0x00 /
0x1C
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
0000 0000
Data Offset Value
0000 0000: Data Offset = 0 BCLK's
0000 0001: Data Offset = 1 BCLK's
…
1111 1110: Data Offset = 254 BCLK's
1111 1111: Data Offset = 255 BCLK's
5.2.29
Page 0 / Register 29: Audio Interface Setting Register 3 - 0x00 / 0x1D
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7-D6
R/W
00
Reserved. Write only default values
D5
R/W
0
Loopback control
0: No Loopback
1: Audio Data in is routed to Audio Data out (DOUT signal on MFP2)
D4
R/W
0
Reserved. Write only default values
D3
R/W
0
Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
D2
R/W
0
Primary BCLK and Primary WCLK Power control
0: Priamry BCLK and Primary WCLK buffers are powered down when the codec is powered down
1: Primary BCLK and Primary WCLK buffers are powered up when they are used in clock
generation even when the codec is powered down
D1-D0
R/W
00
BDIV_CLKIN Multiplexer Control
00: BDIV_CLKIN = DAC_CLK
01: BDIV_CLKIN = DAC_MOD_CLK
10-11: Reserved
5.2.30
Page 0 / Register 30: Clock Setting Register 10, BCLK N Divider - 0x00 / 0x1E
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
BCLK N Divider Power Control
0: BCLK N divider powered down
1: BCLK N divider powered up
84
Register Map
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated