Write 2’b00 to 4/5.32810.15:14 to select SERDES TX clock as RX_CLK output
Write 6’h04 to 4/5.37121.6:0 to set HSTL_DIV2 to value of 4.
Write 16’h0000 to 4/5.36865 SERDES_RATE_CONFIG_TX_RX to set Full Rate
•
Mode Control (Table 2
of the
TLK3134 Datasheet)
o
Write 1’b1 to 4/5.32809.15 XAUI_ORDER
o
Write 1’b0 to 4/5.32808.15 to set source centered data for TX side
o
Write 1’b0 to 4/5.32808.11 to set source centered data for RX side
o
Write 1’b0 to 4/5.32792.1 to disable XAUI data loop back
o
Write 1’b0 to 4/5.32792.0 to disable XGMII data loop back
o
Write 1’b0 to 4/5.0.14 to disable loop back mode
o
Write 3’b110 to 4/5.36874.11:9 to set lane 0 TX swing setting amplitude to 1250 mVdfpp
o
Write 3’b110 to 4/5.36876.11:9 to set lane 1 TX swing setting amplitude to 1250 mVdfpp
o
Write 3’b110 to 4/5.36878.11:9 to set lane 2 TX swing setting amplitude to 1250 mVdfpp
o
Write 3’b110 to 4/5.36880.11:9 to set lane 3 TX swing setting amplitude to 1250 mVdfpp
•
Poll Serdes PLL Status for Locked State
o
Read 4/5.36891.4,0 SERDES_PLL_STATUS – PLL_LOCK_TX/RX
o
Keep polling until both bits are high.
•
Issue Data path Reset
o
Write 1’b1 to 4/5.32800.15
•
Clear Latched Registers
o
Read 4/5.1 XS_STATUS_1 to clear
o
Read 4/5.8 XS_STATUS_2 to clear
o
Read 4/5.32770 TX_FIFO_STATUS to clear
o
Read 4/5.32771 TX_FIFO_DROP_COUNT to clear
o
Read 4/5.32772 TX_FIFO_INSERT_COUNT to clear
o
Read 4/5.32773 TX_CODEGEN_STATUS to clear
o
Read 4/5.(32780,1,2,3) LANE_0~3_EOP_ERROR_COUNT to clear
o
Read 4/5.(32784,5,6,7) LANE_0~3_CODE_ERROR_COUNT to clear
o
Read 4/5.32789 RX_LANE_ALIGN_STATUS to clear
o
Read 4/5.32790 RX_CHANNEL_SYNC_STATUS to clear
o
Read 4/5.32794 RX_CTC_STATUS to clear
o
Read 4/5.32795 RX_CTC_INSERT_COUNT to clear
o
Read 4/5.32796 RX_CTC_DELETE_COUNT to clear
o
Read 4/5.32797 DATA_DOWN to clear
o
Read 4/5.32799 CLOCK_DOWN_STATUS to clear
o
Read 4/5.36891 SERDES_PLL_STATUS to clear
•
Operational Mode Status
o
Read Verify 4/5.1.7 XS_STATUS_1 – Fault (1’b0)
o
Read Verify 4/5.1.2 XS_STATUS_1 – XS Transmit Link Status (1’b1)
o
Read Verify 4/5.8.11 XS_STATUS_2 – Transmit fault (1’b0)
o
Read Verify 4/5.8.10 XS_STATUS_2 – Receive fault (1’b0)
o
Read Verify 4/5.24.12 XS_LANE_STATUS – Align status (1’b1)
o
Read Verify 4/5.24.3:0 XS_LANE_STATUS – Lane (3-0) sync (4’b1111)
o
Read Verify 4/5.32773.6:0 TX_CODEGEN_STATUS (6’b000000)
o
Read Verify 4/5.36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1)
o
Read Verify 4/5.36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1)
22
TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide
SLLU104A - September 2007
