.
Parallel Signals
The parallel signals have on the TLK3134 EVM have been routed to a 0.1” header block that is
configured like the following figure. All RXD pins on all 4 header blocks (RXD[7:0], RXD[15:8],
RXD[23:16], RXD[31:24]), as well as all TXD pins on all 4 header blocks (TXD[7:0], TXD[15:8],
TXD[23:16], TXD[31:24]), have matched trace lengths to them/- 1MIL. Due to routing
constraints RXD[31:0] and TXD[31:0] trace lengths are not matched to each other, but only to
themselves.
Figure 12. Parallel Signal Header Block Example
Parallel Loop back, shown in the following figure, can be easily implemented by placing Jumpers
on the RX/TX pins of the header. For example, placing a jumper on pins 2 and 3 of JMP30 will
loop back TXD7 to RXD7.
Figure 13. Parallel Signal Header Block Example
7
1
RXD 7:0
VDD
TX
GND
TX
RX
GND
43
37
13 19 25 31
12
6
48
42
18 24 30 36
PARALLEL
LOOPBACK
TXD 7:0
JM
P30
TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide
19
SLLU104A - September 2007
