.
XAUI Mode (XGMII) Test and Setup Configuration
The device reset requirements and setup procedure to configure the TLK3134 for XAUII Mode
(XGMII) is as follows:
REFCLK frequency = 156.25 MHz, Serdes Data Rate = Full Rate, Mode = Transceiver,
Edge Mode = Source Centered, RX_CLK out = TXBCLK, Jitter Cleaner PLL Multiplier Ratio = 1X or Off
•
Device Pin Setting(s) – Pin settings allow for maximum software configurability.
o
Ensure ST input pin is Low.
o
Ensure CODE input pin is Low.
o
Ensure PLOOP input pin is Low.
o
Ensure SLOOP input pin is Low.
o
Ensure SPEED [1:0] input pins are both High.
o
Ensure ENABLE input pin is High.
o
Ensure PRBS_EN input pin is Low.
•
Reset Device
o
Issue a hard or soft reset (RST_N asserted for at least 10 us -or- Write 1’b1 to 4/5.0.15)
•
Clock Configuration
o
If using JCPLL (JCPLL 1X)
JCPLL Mux Settings (Figure 3
of the TLK3134 Datasheet)
Select REFCLK input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b01 to 4/5.37120.15:14
•
If Differential REFCLK used – Write 2’b00 to 4/5.37120.15:14
Write 2’b11 to 4/5.37120.13:12 to select differential REFCLKP/N as RXBYTECLK
Write 4’b0000 to 4/5.37120.11:8 to select jitter cleaned clock for SERDES TX/RX.
Write 2’b00 to 4/5.37120.5:4 to select jitter cleaned clock for HSTL VTP 2x
Write 2’b00 to 4/5.32810.15:14 to select SERDES TX clock as RX_CLK output
Write 16’h0081 to 4/5.37126 to set Charge pump control
Write 16’h0080 to 4/5.37128 to set TXRX output divider
Clock Divide Settings (Table 211
of the
TLK3134 Datasheet)
Write 7’b1000000 to 4/5.37124.14:8 to set REF_DIV to value of 1
Write 1’b1 to 4/5.37124.15 REFDIV_EN to enable reference clock divider
Write 7’h14 to 4/5.37124.6:0 to set FB_DIV to value of 20
Write 1’b1 to 4/5.37124.7 FBDIV_EN to enable feedback divider
Write 7’h14 to 4/5.37125.6:0 to set RXTX_DIV to value of 20
Write 1’b1 to 4/5.37125.7 OUTDIV_EN to enable output divider
Write 7’h0D to 4/5.37121.14:8 to set HSTL_DIV to value of 13
Write 7’h06 to 4/5.37121.6:0 to set HSTL_DIV2 to value of 6
Write 15’h1515 to 4/5.36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier factor to 10
Write 16’h0000 to 4/5.36865 SERDES_RATE_CONFIG_TX_RX to set Full Rate
Write 1’b1 to 4/5.37127.15 to enable Jitter Cleaner
Wait 2 ms in order for JCPLL to lock
o
If using clock bypass mode (JCPLL Off)
JCPLL Mux Settings (Figure 3
of the
TLK3134 Datasheet)
Select REFCLK input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b01 to 4/5.37120.15:14
•
If Differential REFCLK used – Write 2’b00 to 4/5.37120.15:14
Select RXBYTE_CLK (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.13:12
•
If Differential REFCLK used – Write 2’b11 to 4/5.37120.13:12
Select SERDES TX Reference Clock Input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.11:10
•
If Differential REFCLK used – Write 2’b11 to 4/5.37120.11:10
Select SERDES RX Reference Clock Input (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.9:8
•
If Differential REFCLK used – Write 2’b11 to 4/5.37120.9:8
Select HSTL_2X_CLK (Default = Differential)
•
If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.5:4
•
If Differential REFCLK used – Write 2’b11 to 4/5.37120.5:4
TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide
21
SLLU104A - September 2007