Texas Instruments TLK3134 XAUI, User Manual

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• If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.9:8
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.9:8
ƒ
Select DELAY_CLK (Default = Differential)
• If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.7:6
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.7:6
ƒ
Select HSTL_2X_CLK (Default = Differential)
• If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.5:4
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.5:4
ƒ
Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output (per channel)
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Write 6’h04 to 4/5.37121.6:0 to set HSTL_DIV2 to value of 4.
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Write 15’h1515 to 4/5.36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier factor to 10
ƒ
Write 16’h5555 to 4/5.36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
• Mode Control (Table 2 of the TLK3134 Datasheet)
o
Write 1’b0 to 17.0 for RX source centered mode (per channel)
o
Write 1’b0 to 17.1 for TX source centered mode (per channel)
o
Write 1’b1 to 17.2 to enable 8B/10B encode decode functions (per channel)
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Write 1’b1 to 17.3 to enable 1000Base-X PCS TX & PCS RX functions (per channel)
o
Write 1’b1 to 17.4 to set nibble order, LSB on rising edge, MSB on falling edge (per channel)
o
Write 1’b1 to 17.5 to enable DDR data on TX/RX directions (per channel)
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Write 1’b0 to 17.6 to disable FC_PH overlay detection (per channel)
o
Write 1’b1 to 17.7 to enable comma detection (per channel)
o
Write 1’b0 to 17.9 to disable full DDR mode (per channel)
o
Write 1’b0 to 16.8 to disable Farend Loop back (per channel)
o
Write 1’b0 to 0.14 to disable loop back mode (per channel)
o
Write 3’b111 to 4/5.36874.11:9 to set channel 0 TX swing setting amplitude to 1375 mVdfpp
o
Write 3’b111 to 4/5.36876.11:9 to set channel 1 TX swing setting amplitude to 1375 mVdfpp
o
Write 3’b111 to 4/5.36878.11:9 to set channel 2 TX swing setting amplitude to 1375 mVdfpp
o
Write 3’b111 to 4/5.36880.11:9 to set channel 3 TX swing setting amplitude to 1375 mVdfpp
• Poll Serdes PLL Status for Locked State
o
Read 4/5.36891.4,0 SERDES_PLL_STATUS – PLL_LOCK_TX/RX
o
Keep polling until both bits are high.
• Issue Data path Reset
o
Write 1’b1 to 16.11 (per channel)
• Clear Latched Registers
o
Read 1 PHY_STATUS_1 to clear (per channel)
o
Read 18 PHY_RX_CTC_FIFO_STATUS to clear (per channel)
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Read 19 PHY_TX_CTC_FIFO_STATUS to clear (per channel)
o
Read 28 PHY_CHANNEL_STATUS to clear (per channel)
o
Read 4/5.36891 SERDES_PLL_STATUS to clear
• Operational Mode Status
o
Read Verify 1.2 PHY_STATUS_1 – Link Status (1’b1) (per channel)
o
Read Verify 18.15 PHY_RX_CTC_FIFO_STATUS – RX_CTC_Reset (1’b0) (per channel)
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Read Verify 19.15 PHY_TX_CTC_FIFO_STATUS – TX_FIFO_Reset_1Gx (1’b0) (per channel)
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Read Verify 28.13:12 PHY_CHANNEL_STATUS – Enc/Dec Invalid Code Word (2’b00) (per channel)
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Read Verify 4/5.36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1)
o
Read Verify 4/5.36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1)
TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide
25
SLLU104A - September 2007