System Overview
8
TIDUES1A – October 2019 – Revised February 2020
Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 (
≤
12.95 W) PoE-PD
2.3
Highlighted Products
The EMC Compliant 10/100 Mbps Ethernet PHY reference design with IEEE 802.3at Type-1 (
≤
12.95 W)
PoE-PD features the following devices:
PSE side board (Board-1):
•
TPS23861: Quad IEEE 802.3at Power-Over-Ethernet PSE controller
•
DP83825I: Low-power 10/100 Mbps Ethernet physical layer transceiver
•
DP83822I: Robust low-power 10/100 Ethernet physical layer (PHY) transceiver
•
ESDS312: 3.6-V Data-line surge and 30-kV ESD protection diode array
•
TPS7A2633: 500-mA, 18-V, low-I
Q
low-dropout (LDO) linear regulator with power good
•
MSP430F5529: 25-MHz MCU with integrated USB PHY, 128KB Flash, 8KB RAM, 12-bit, 14-channel
ADC, 32-bit hardware multiplier
•
LM3478: 2.97-V to approximately 40-V wide-input range Boost, SEPIC, Flyback DC/DC Controller
•
LP5907: 250-mA ultra-low-noise, low-I
Q
low-dropout (LDO) linear regulator
•
LM5160: Wide input 65-V, 2-A synchronous buck, Fly-Buck™ converter
•
TPS7A4001: 100-V input, 50-mA, single output low-dropout linear regulator
PD side board (Board-2):
•
TPS23755: IEEE 802.3at PoE PD with no-opto flyback DC/DC controller
•
DP83825I: Low-power 10/100 Mbps Ethernet physical layer transceiver
•
ESDS312: 3.6-V, data-line surge and 30-kV ESD protection diode array
•
TPS2121: 2.7–22 V, 56-m
Ω
, 4.5-A, priority power MUX with seamless switchover
•
TPS7A26: 500-mA, 18-V low-I
Q
low-dropout (LDO) linear regulator with power good
•
MSP430F5529: 25-MHz MCU with integrated USB PHY, 128KB Flash, 8KB RAM, 12-bit, 14-channel
ADC, 32-bit hardware multiplier
For more information on each of these devices, see their respective product folders at www.ti.com.
2.4
System Design Theory
2.4.1
Reduced Media Independent Interface (RMII)
For space-critical designs, the DP83825I 10/100 Mbps single port Physical Layer device incorporates the
low pin count Reduced Media Independent Interface (RMII) as specified in the RMII specification. The
RMII provides a lower pin count alternative to the IEEE 802.3 defined Media Independent Interface (MII)
for connecting the DP83825I PHY to a MAC or another PHY in back-to-back or repeater mode in 10/100
Mbps systems. It allows the designer to minimize the cost of the system design while maintaining all the
features of the IEEE 802.3 specification. The Ethernet standard (IEEE 802.3u) defines the MII with 16 pins
per port for data and control (8 data lines and 8 control signals). The RMII specification reduces the data
interfaces from 4-bit data to 2-bit data. In addition, control is reduced to 3 signals. Thus, the total signal
connection is reduced to 7 pins (8 pins if RX_ER is required by the MAC).
This reference design does not include a media access controller (MAC) on PD side board. Therefore, the
RMII signals of the DP83825I device terminate at pin header J6 for RMII external loopback. Since the
RMII transmit and receive signals are synchronous to the same clock, it is possible to implement a remote
loopback using external connections. This operation allows diagnostic testing where it may be desirable to
receive data on the physical media and loop that data back to the transmitter, providing a remote loopback
for the far-end link partner. The following connections need to be made external to the DP83825 device:
•
Connect RXD[1:0] to TXD[1:0]
•
Connect RX_DV to TX_EN
Although RMII is synchronous bus architecture, there are a number of factors limiting signal trace lengths.
RMII signals are single-ended signals and the recommendations for reducing the effects of digital I/O
noise coupling include:
•
With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible
