System Description
3
TIDUES1A – October 2019 – Revised February 2020
Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 (
≤
12.95 W) PoE-PD
1.1
Key System Specifications
This reference design targets the following specifications and features as given in
Table 1. Key System Specifications
PARAMETER
SPECIFICATIONS
Ethernet PHY
DP83825I - low power 10/100 Mbps Ethernet physical layer transceiver in ultra-small form-
factor 24-pin 3 mm × 3 mm QFN package
Cable reach
150 m for data only; 100 m for power + data together
Number of ports
Power sourcing equipment (PSE) side board:
Two ports - one port to connect with IXIA,
the second port with PoE-PSE to inject power;
Powered delivery (PD) side board:
One port with PoE-PD
MAC interface
RMII(Master and Slave mode)
Termination
Integrated MDI and MAC termination resistors
Status LED
Two LEDs (Link and activity with option to configure as PU or PD)
Clock
25-MHz crystal with internal oscillator
USB virtual COM port
Onboard MSP430F5529 MCU to access to PHY registers
PHY configuration
Through-strap resistors
Power
PSE side board:
12 V DC;
PD side board:
IEEE 802.3at Type-1 PoE or 12 V DC
Bit error rate (BER)
No more than 10
–11
with less than a 5% chance of error as per Fast Ethernet Consortium
Physical Medium Dependent (PMD) Clause 25 Test Suite #25.2.4
Radiated emission
Pre-compliance tested for CISPR 22 (EN 55022) (30 MHz to 1 GHz) meets both class A and
B limits; FCC Part 15 subpart B (30 MHz to 1 GHz) meets both class A and B limits
ESD
Pre-compliance tested for IEC61000-4-2 ESD ±12-kV contact and ±15-kV Air discharge
meets criterion B
EFT
Pre-compliance tested for IEC61000-4-4 EFT ±2-kV IO capacitive coupling meets criterion B
Temperature range
Industrial: –40°C to 85°C