System Overview
6
TIDUES1A – October 2019 – Revised February 2020
Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 (
≤
12.95 W) PoE-PD
The IXIA network emulator generates the network traffic that is pushed in to the data input port through
RJ45 connector (J9) of the PSE side board. These Ethernet packets are received by the Ethernet PHY
DP83822I device , which is connected in RMII back-to-back mode (repeater mode) with another Ethernet
PHY DP83825I device. The PSE side board has a local MCU for USB-2-MDIO conversion.
Both Ethernet PHYs (DP83822I and DP83825I) share the common serial management interface (SMI)
providing access to the internal registers of the PHY for configuration and status information. Therefore, to
distinguish between Ethernet PHYs, the DP83825I and DP83822I devices are assigned different PHY
address – 00 and 01, respectively, which is determined by latching the PHY address configuration pins
during the power-up or hardware reset. In repeater mode or RMII back-to-back mode, one Ethernet PHY
acts as a RMII master and the other Ethernet PHY as RMII slave.
In this reference design, the DP83822I device is made RMII slave and the DP83825I device as RMII
master. In RMII slave mode, a 50-MHz clock input must be supplied to the DP83822I device on XI pin that
comes from the clock output of the DP83825I device. The Ethernet packets received by the DP83822I
device are sent over the RMII to the DP83825I device, which are then transmitted out from the RJ45
connector (J8) over a 150-m Ethernet cable after injecting power to the PD side board.
The PSE side board is equipped with the necessary circuitry to inject PoE, which includes a boost
converter (LM3478) to generate 48-V DC from 12-V DC input supply and a PoE-PSE device. The
TPS23861 device is an IEEE 802.3at quad port PSE controller. However, this reference design needs
only one PSE port and other ports are terminated properly as per device recommendations. The
TPS23861 device automatically detects PDs that have a valid signature, determines power requirements
according to classification, and applies power.
On the PD side board, the power is received by the TPS23755 IEEE 802.3at PoE-PD device with an
integrated Flyback DC/DC converter generating isolated 12-V DC as an input to point-of-loads (POLs)
power supplies and data is received by the DP83825I Ethernet PHY. The received network traffic is then
looped-back either internally from the DP83825I device or externally to the PSE side board. From there,
loopback packets finally reach the IXIA tool where they are compared with the generated packet for
successful reception. There are several loopback options within the DP83825I device that test and verify
various functional blocks within the PHY. Enabling loopback modes allow for in-circuit testing of the digital
and analog data paths.
The DP83825I device may be configured to any one of the near-end loopback modes or to the far-end
(reverse) loopback mode. MII Loopback is configured using the Basic Mode Control Register (BMCR,
address 0x0000). All other loopback modes are enabled using the BIST Control Register (BISCR, address
0x0016).
