Adapter Internal Registers
A-26
Table A–10. Network Status Register Bits (Continued)
Bit
Name
Function
20
RXSTOP
Receiver stopped: This bit indicates the completion of a receive STOP command.
This bit is cleared by writing a 1 to its bit position. Writing a 0 has no effect.
19 – 16
Reserved
A.3.4 Network Status Mask Register – NetMask @ 0x00 (DIO)
This register determines whether network status flags in the NetSts register
cause interrupts or not. Each bit in this register acts as a mask on the corre-
sponding NetSts register bit. If the mask bit is set, then an interrupt is raised
if the corresponding status flag is set. All bits in this register are set to 0 on an
Ad_Rst or when PRST# is asserted.
24
25
26
27
28
29
30
31
Reserved
MASK4
MASK5
MASK6
MASK7
Byte 3
Table A–11. Network Status Mask Register Bits
Bit
Name
Function
31
MASK7
MII interrupt mask: When this bit is set, a network status interrupt is posted if the MIRQ
bit in the NetSts register is set.
30
MASK6
Heartbeat error mask: When this bit is set, a network status interrupt is posted if the
HBEAT bit in the NetSts register is set.
29
MASK5
Transmit stop mask: When this bit is set, a network status interrupt is posted if the
TXSTOP bit in the NetSts register is set.
28
MASK4
Receive stop mask: When this bit is set, a network status interrupt is posted if the
RXSTOP bit in the NetSts register is set.
27 – 24
Reserved
Summary of Contents for ThunderLAN TNETE100A
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