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Texas Instruments ThunderLAN TNETE100A Programmer'S Manual Download Page 137

Adapter Internal Registers

A-24

 

Table A–8.  Network Command Register Bits (Continued)

Bit

Name

Function

0

TXPACE

Transmit pacing (CSMA/CD): This bit allows pacing of transmitted CSMA/CD frames to
improve network utilization of network file servers. When this bit is set, the pacing algo-
rithm is enabled. When this bit is cleared, the pacing algorithm is disabled.

The pacing algorithm automatically delays new adapter frame transmissions in conten-
tion situations. If a transmitted frame either collides with another frame or has to defer
to another transmission, a pacing delay of four interframe gaps (4*96 bit-times) is in-
serted between new frame transmissions. This pacing delay continues to be inserted
until 31 sequential frames are transmitted without collision or deference.

A.3.2 Network Serial I/O Register – NetSio @ 0x00 (DIO)

This register shares control of the external EEPROM interface with the PCI
NVRAM register. Control of the EEPROM interface swaps between these two
control registers on a most-recently-written basis. Whenever the PCI NVRAM
register is written to, it takes control of the EEPROM interface pins. Whenever
the DIO_DATA register is written to, the NetSio register takes control of the
EEPROM interface pins. On reset (software or hardware), control of the inter-
face is given to the PCI NVRAM register. All bits in this register are set to 0 on
an Ad_Rst or when PRST# is asserted.

8

9

10

11

12

13

14

15

MDATA

MTXEN

MCLK

NMRST

EDATA

ETXEN

ECLOK

MINTEN

Byte 1

Table A–9.  Network Serial I/O Register Bits

Bit

Name

Function

15

MINTEN

MII Interrupt enable: When this bit is set to 1, the MIRQ interrupt bit is set if the MDIO
pin is asserted low.

14

ECLOK

EEPROM SIO clock: This bit controls the state of the EDCLK pin. When this bit is set
to 1, EDCLK is asserted. When this bit is set to 0, EDCLK is deasserted.

This bit is also used to determine the state of the EEPROM interface. If the EEPROM
port is disabled, this bit is always read as 0, even if a value of 1 is written to the bit.
ThunderLAN detects that the EEPROM port is disabled by sensing the state of the
EDCLK pin during reset. If the EDCLK pin is read as 0 during reset (due to an external
pulldown resistor), then the EEPROM interface is disabled and no attempt is made to
read configuration information.

13

ETXEN

EEPROM SIO transmit enable: This bit controls the direction of the EDIO pin. When this
bit is set to 1, EDIO is driven with the value in the EDATA bit. When this bit is set to 0,
the EDATA bit is loaded with the value on the EDIO pin.

Summary of Contents for ThunderLAN TNETE100A

Page 1: ...ThunderLAN TNETE100A TNETE110A TNETE211 Programmer s Guide October 1996 Network Business Products ...

Page 2: ...Printed in U S A October 1996 L411001 9761 revisionA SPWU013A ...

Page 3: ......

Page 4: ...ThunderLANt Programmer s Guide TNETE100A TNETE110A TNETE211 Literature Number SPWU013A Manufacturing Part Number L411001 9761 revision A October 1996 ...

Page 5: ...DUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applica...

Page 6: ...rom an attached physical interface PHY to the host Chapter 2 ThunderLAN Registers shows how to access the various ThunderLAN registers and how to use these registers to access external devices attached to ThunderLAN Chapter 3 Initializing and Resetting discusses how to initialize and reset the controller and the attached PHYs Chapter 4 Interrupt Handling describes what happens when interrupts occu...

Page 7: ...ges of IEEE Standard 802 12 MAC Parameters Physical Layer Medium Attachment Units and Repeater for 100 Mb s Operation Draft 5 0 of the Supplement to 1993 version of ANSI IEEE Std 802 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method Physical Layer Specifications PCI Local Bus Specification Revision 2 0 is the specification which ThunderLAN is designed to meet To obtain...

Page 8: ...om Deutsch 49 8161 80 33 11 or 33 1 30 70 11 68 English 33 1 30 70 11 65 Francais 33 1 30 70 11 64 Italiano 33 1 30 70 11 67 EPIC Modem BBS 33 1 30 70 11 99 European Factory Repair 33 1 93 22 25 40 Europe Customer Training Helpline Fax 49 81 61 80 40 10 Asia Pacific Literature Response Center 852 2 956 7288 Fax 852 2 956 2200 Japan Product Information Center 0120 81 0026 in Japan Fax 0120 81 0036 ...

Page 9: ...Trademarks vi Trademarks Ethernet is a trademark of Xerox Corporation ThunderLAN and Adaptive Performance Optimization are trademarks of Texas Instruments Incorporated ...

Page 10: ...EEPROM Map 2 30 3 Initializing and Resetting 3 1 3 1 Initializing 3 2 3 1 1 Finding the Network Interface Card NIC 3 2 3 1 2 Finding the Controller in Memory and I O Space 3 4 3 1 3 Finding Which Interrupt was Assigned 3 5 3 1 4 Turning on the I O Port and Memory Address Decode 3 6 3 1 5 Recovering the Silicon Revision Value 3 7 3 1 6 Setting the PCI Bus Latency Timer 3 7 3 2 Resetting 3 8 3 2 1 H...

Page 11: ...ormat 6 2 6 1 2 Transmit Tx Frame Format 6 3 6 2 GO Command 6 4 6 2 1 Starting Frame Reception Rx GO Command 6 4 6 2 2 Starting Frame Transmission Tx GO Command 6 6 7 Physical Interface PHY 7 1 7 1 MII Enhanced Interrupt Event Feature 7 2 7 2 Nonmanaged MII Devices 7 7 7 3 Bit Rate Devices 7 8 7 4 PHY Initialization 7 9 A Register Definitions A 1 A 1 PCI Configuration Registers A 2 A 1 1 PCI Autoc...

Page 12: ...etwork Configuration Register NetConfig 0x04 DIO A 27 A 3 6 Manufacturing Test Register ManTest 0x04 DIO A 29 A 3 7 Default PCI Parameter Registers 0x08 0x0C DIO A 29 A 3 8 General Address Registers Areg_0 3 0x10 0x24 DIO A 30 A 3 9 Hash Address Registers HASH1 HASH2 0x28 0x2C DIO A 31 A 3 10 Network Statistics Registers 0x30 0x40 DIO A 32 A 3 11 Adapter Commit Register Acommit 0x40 DIO Byte 3 A 3...

Page 13: ...6 B 2 1 PHY Generic Control Register GEN_ctl 0x0 B 7 B 2 2 PHY Generic Status Register GEN_sts 0x1 B 8 B 2 3 PHY Generic Identifier GEN_id_hi GEN_id_lo 0x2 0x3 B 9 B 2 4 ThunderLAN PHY Identifier High Low TLPHY_id 0x10 B 9 B 2 5 ThunderLAN PHY Control Register TLPHY_ctl 0x11 B 9 B 2 6 ThunderLAN PHY Status Register TLPHY_sts 0x12 B 11 C TNETE100PM TNETE110PM C 1 ...

Page 14: ... 9 Transmit CSTAT Complete Fields 5 14 6 1 Token Ring Logical Frame Format Rx 6 2 6 2 Ethernet Logical Frame Format Rx 6 2 6 3 Token Ring Logical Frame Format Tx 6 3 6 4 Ethernet Logical Frame Format Tx 6 3 7 1 100VG AnyLAN Support Through ThunderLAN s Enhanced 802 3u MII 7 2 7 2 MII Frame Format Read 7 3 7 3 MII Frame Format Write 7 4 7 4 Assertion of Interrupt Waveform on the MDIO Line 7 6 7 5 W...

Page 15: ...er Bits A 10 A 5 Host_CMD Register Bits A 12 A 6 HOST_INT Register Bits A 18 A 7 DIO_ADR Register Bits A 19 A 8 Network Command Register Bits A 23 A 9 Network Serial I O Register Bits A 24 A 10 Network Status Register Bits A 25 A 11 Network Status Mask Register Bits A 26 A 12 Network Configuration Register Bits A 27 A 13 MAC Protocol Selection Codes A 29 A 14 Ethernet Error Counters A 33 A 15 Dema...

Page 16: ...s A 25 ThunderLAN PHY Status Register Bits A 50 B 1 PHY Generic Control Register Bits B 7 B 2 PHY Generic Status Register Bits B 8 B 3 ThunderLAN PHY Control Register Bits B 10 B 4 ThunderLAN PHY Status Register Bits B 11 ...

Page 17: ...xiv ...

Page 18: ...lar support for the 100 Base T IEEE 802 3u and 100VG AnyLAN IEEE 802 12 is provided via a media independent interface MII The TNETE110A is the same device without the MII and is 10M bps only ThunderLAN uses a single driver suite to support mul tiple networking protocols ThunderLAN architecture was designed to achieve the following goals High performance with low use of host CPU Simplicity of desig...

Page 19: ...mit channels provide independent host channels for these two priority types CSMA CD protocols only support a single frame priority but the two channels can be used to prioritize network access if needed All received frames pass through the single receive channel ThunderLAN s multiplexed SRAM is 3 375K bytes in size This allows it to sup port one 1 5K byte FIFO for receive two 0 75K byte FIFOs for ...

Page 20: ...e software used to transmit frames re ceive frames and service the PHY events It accomplishes this by integrating time consuming tasks into the controller These tasks include The DMA of data into and out of the controller A simplified interrupt driven frame buffer management technique The elimination of PHY register polling through MII interrupts DMA of data is handled through list structures Thun...

Page 21: ... 0 signals 0x7h memory write 0xCh memory read multiple 0xEh memory read line ThunderLAN responds to the following PCI cycles when acting in slave mode on the PCI bus 0x2h I O read 0x3h I O write 0x6h memory read 0x7h memory write 0xAh configuration read 0xBh configuration write 0xCh memory read multiple 0xEh memory read line 0xFh memory write and invalidate Future versions of ThunderLAN may not be...

Page 22: ...15 byte 2 uses bits 16 23 byte 3 uses bits 24 31 Figure 1 2 PCI Bus Byte Assignment Byte 0 Byte 1 Byte 2 Byte 3 0 7 8 15 16 23 24 31 ThunderLAN uses the full four bytes per data cycle The only exception is when the data to be transferred is not octet aligned In this case the PCI controller might not transfer the full four bytes on the first cycle ThunderLAN deasserts the IRDY signal only once if n...

Page 23: ...1 6 ...

Page 24: ...HY devices at tached to the MII They must be accessed as well for transmission initiation and reception of data Other activities which require the user to understand ThunderLAN s register spaces include determining the cause of event driven interrupts and how to clear them and diagnostic functions This chapter ex plains register configurations and discusses control of these spaces through code exa...

Page 25: ...pace directly on the PCI bus The beginning address is determined by the value written into the PCI configuration space base ad dress registers Once the base register s address is determined ThunderLAN reads and writes to these registers like ordinary memory or I O ports Since the ThunderLAN devices are directly connected to the PCI there is no external decode logic that generates a chip select all...

Page 26: ...io register which is lo cated in the internal DIO register space Control registers on the PHY side of the MII management interface can be similarly written and read through the NetSio register A BIOS ROM can be enabled via the BRE bit in the PCI BIOS ROM base ad dress register and its chip selected address dynamically assigned via a base register in the configuration space The BRE bit points to a ...

Page 27: ...eserved 00h Reserved 00h Reserved 00h IntDis Reserved 00h Reserved 00h PCI NVRAM Reserved 00h 48h B4h read only 2Ch Reserved 00h Reserved 00h Register configuration space information fields are needed to identify a board in a slot to a driver The functional purpose of the board the manufacturer the revision and several bus requirements can be obtained by inspecting these parameters The PCI configu...

Page 28: ...ese short slot dependent address spaces appear to the host processor The shaded registers in Figure 2 3 can be autoloaded from an external serial EEPROM Check the following before accessing the PCI configuration space Ensure that there is a PCI BIOS present or other support for BIOS calls Ensure that the BIOS is the right revision Use a PCI BIOS call to find all attached devices on the PCI bus Mak...

Page 29: ...e the bits in the memory base address register and the I O base address register which indicate the space size al location required to access the host registers are hardwired in the Thunder LAN controllers Some of the allowed PCI configuration space values like base registers beyond the basic I O and memory base registers are not implement ed because no other entities are supported by this PCI int...

Page 30: ...ndicates a networking card and the vendor ID is the manufacturer code These values can be overlaid in the configuration space with values from the EEPROM during the autoconfigura tion These should be available to the driver software either in the BIOS ROM or on machine readable media supplied with the network board s The following example reads a byte of a PCI register PciRdByte Read a byte from P...

Page 31: ... read Return val WORD value read WORD PciRdWord WORD devid WORD addr union REGS r r h ah PCI_FUNCTION_ID r h al READ_CONFIG_WORD r x bx devid r x di addr int86 PCI_INT r r return r x cx This code passes an address 10 if the driver regards the host registers as memory locations ThunderLAN s first base address register is hardwired as a memory base register or 14 if the driver treated the host regis...

Page 32: ...RM register is used to give the physical addresses of a transmit or receive list to ThunderLAN s direct memory access DMA controller Thun derLAN uses the address in the CH_PARM register to DMA data into or out of its FIFOs In an adapter check an error condition where ThunderLAN must be reset CH_PARM contains information on the nature of the error The HOST_INT register contains information on the t...

Page 33: ...ration base register both with the four LSBs in these registers fixed to indicate the field width requested be reserved in the respective address space for the host reg ister block four quad words or 16 bytes The rest of the bits of a base register are filled in by the O S after all the space requests are considered Assigning space in this way assures that all starts of fields are naturally aligne...

Page 34: ...to 40 Areg_3 39 to 32 Areg_3 47 to 40 Areg_2 39 to 32 Areg_2 31 to 24 Areg_2 23 to 16 Areg_2 31 to 24 Areg_1 23 to 16 Areg_1 15 to 8 Areg_1 7 to 0 Areg_1 15 to 8 Areg_0 7 to 0 Areg_0 47 to 40 Areg_1 39 to 32 Areg_1 47 to 40 Areg_0 39 to 32 Areg_0 31 to 24 Areg_0 23 to 16 Areg_0 revision Default Subclass Default Min_Lat Default Max_Lat Default LSbyte vendor ID Default MSbyte vendor ID Default LSbyt...

Page 35: ...interrupt The bits in the NetMask register are used to mask whether the status flags in NetSts cause interrupts or not The NetConfig register sets network configuration options during reset This register can only be written to when ThunderLAN is in reset NRESET 0 It allows the controller to receive CRCs RxCRC pass errored frames PEF use a one fragment list on receive refer to subsection 5 3 One Fr...

Page 36: ...ue read BYTE DioRdByte WORD base_addr WORD addr outpw base_addr OFF_DIO_ADDR addr return inp base_addr OFF_DIO_DATA addr 3 The address of the register being read is determined by the calling program and is passed to this routine as a parameter along with the the I O base ad dress An output is executed to the DIO_ADR host register as part of setting up the pointer address In x86 architectures there...

Page 37: ...D base address of TLAN internal registers addr WORD address to read Return val DWORD value read DWORD DioRdDword WORD base_addr WORD addr DWORD data addr 0x3fff outpw base_addr OFF_DIO_ADDR addr data DWORD inpw base_addr OFF_DIO_DATA 0x0000ffffl data DWORD inpw base_addr OFF_DIO_DATA 2 16l return data ...

Page 38: ...lso be implemented Within the ex tended set 0x02 through 0x07 are defined and 0x08 through 0x0F are re served The area between 0x10 and 0x1F can be used for vendor specific ap plications The basic set of registers is shown in dark gray above The ex tended registers are shown in lighter gray and white The light gray registers are those defined by 802 3 and the white registers are vendor specific Th...

Page 39: ... PHY that you are using Writing to a register in a PHY through the management interface involves writ ing data and clock bits into NetSio an internal register which uses the pointer host registers The data unit to or from a PHY register is always 16 bits The NetSio register uses three bits to drive the MDIO MDCLK MII manage ment interface These bits are MCLK MTXEN and MDATA These bits directly con...

Page 40: ...on the MDIO pin Once this is done an access can be done with a two bit start delimiter then a two bit op code for read or write followed by five bits of PHY address five bits of register address two bits of turnaround time in case the PHY is going to write to the data line and 16 bits of data The synchronization code could be done this way MIISync send MII synchronization pattern to all possible M...

Page 41: ...ay define set x DioWrByte base_addr Net_Sio BYTE DioRdByte base_addr Net_Sio x The routine to synchronize the PHYs is part of the startup code The controller at this point is held in reset due to the drivers writing a 1 to the Ad_Rst bit bit 15 in the HOST_CMD register or a reset being received on power up through the PCI system Setting the NMRST bit to 0 places the MII bus in a reset state for i ...

Page 42: ...ORD pval mread array 01 is the start delimiter sequence for the MII interface 10 specifies the operation will be a read See IEEE 802 3u WORD i tmp char ack BYTE b WORD diodata base_addr OFF_DIO_DATA Net_Sio CritOn outpw base_addr OFF_DIO_ADDR Net_Sio This example uses the host registers as I O ports so the code needs to resolve a pointer to the host NetSio register NetSio is added to the base DIO_...

Page 43: ...two active byte strobe out of four write cycle The DIO_ADR register is 16 bits in width b inp diodata b MINTEN b MDATA b MCLK outp diodata b This cycle reads modifies and writes the contents of the NetSio register It turns off the MII interrupt by forcing the MINTEN bit to a logic low makes sure the data bit in the interface comes on with a logic low when enabled in the next write and makes sure t...

Page 44: ...MCLK outp diodata b 1 b MDATA outp diodata b togLH b MCLK outp diodata b b MCLK outp diodata b 0 10 is the read op code for an MII management operation Send the device number Internal 31 0x1f External 0 0x00 for i 0x10 i i 1 10 is the read op code if i dev b MDATA else b MDATA outp diodata b togLH b MCLK outp diodata b b MCLK outp diodata b The following loop index is used as a mask to walk throug...

Page 45: ...utp diodata b togLH b MCLK outp diodata b b MCLK outp diodata b 802 3u specifies an idle bit time after the register address is sent This and the following zero bit are designated as Turn around cycles b MTXEN outp diodata b To get an idle bit turn off the data driver then cycle the clock togLH b MCLK outp diodata b end turn around cycle b MCLK outp diodata b this should clock 0 ackn bit out b MCL...

Page 46: ...loop variable as a mask for pointing to the bit position stored The MSB comes in first For each shift cycle the clock goes up to start the access and goes down to guarantee that some time elapses between the rising edge of the clock and the time the data is sampled b MCLK outp diodata b if inp diodata MDATA tmp i if data bit 1 or position in b MCLK outp diodata b else If the PHY does not respond o...

Page 47: ...e read and write op erations the PHY is not able to assert the MDIO pin low to indicate a PHY inter rupt After this cycle and a read the driver sets the MINTEN bit high which en ables PHY interrupts set MINTEN pval tmp CritOff The function value returned is reserved for completion and error codes and is returned via a pointer CritOff turns on the interrupts again and is defined as define CritOff i...

Page 48: ...ct as an input bus when accepting the data from the EPROM which is sig naled by the EOE EPROM output enable strobe This interface is designed to support all types of read cycles from the host byte word and long word Four cycles are automatically done to prepare a 32 bit response to the PCI read cycle During the state machine s execution the PCI read cycle sends wait states to the host processor Wr...

Page 49: ... space Any time this register is written to control of the EDIO EDCLK bus reverts back to this register The other possible source of values for this bus is from an internal register the network serial I O register NetSio Here the three bits used to control the inter face are EDATA ETXEN and ECLOK The PCI_ NVRAM register interface to this external EEPROM port was designed assuming that there might ...

Page 50: ...EeRdByte read byte of data from EEPROM see Exel XL24C02 device specification Parameters base_addr WORD base address of TLAN internal registers addr WORD address to read Return val BYTE value read BYTE EeRdByte WORD base_addr WORD addr int i ips tmp CritOn CritOn turns off the interrupts Remember that there are two possible control points for reading and writing to the EEPROM This is an attempt to ...

Page 51: ... and write command on bus sel base_addr WRITE The EEPROM with its serial interface must receive a wakeup pattern and a device number since more than one device can be tied to this bus This code assumes that there is only one device 0 EEPROM should have acked if ack base_addr return 0 send address on EEPROM to read from sendaddr base_addr addr sendaddr is a routine for serially sending out the addr...

Page 52: ...e DIO_ADR and DIO_DATA registers in the host register block send EEPROM stop access sequence clr EDATA set ECLOK set EDATA clr ETXEN The following control signal movements are specified in the data sheet for the EEPROM CritOff return BYTE tmp 0xff Similar routines can be created for writing a byte reading and writing a word or reading and writing a double word to the EEPROM using the NetSio regis ...

Page 53: ... 0 7 b Local loopback select d ThinNet select 0x71 0x33 ttttrrrr Transmit and receive burst size control tttt Transmit burst size control 0 7 rrrr Receive burst size control 0 7 0x72 0x00 ccccbbbb PHY TLPHY_ctl register initialization options cccc Bits 15 12 of the MII register 0x11 TLPHY_ctl bbbb Bits 3 0 of the MII register 0x11 TLPHY_ctl 0x73 0x0f Interrupt pacing timer value 0x74 0xff Configur...

Page 54: ...type L Ignore last byte plus one DMA no write test F Zero ignore bits 12 and 13 of Rx length request T Token ring format request A AT T2X01 fix enable receive logic state machine tweak D Stop on first error P PMI wrap length check disable request 0x7b 0x05 Test to execute 1 Multicast test 2 Pipe test 3 Mix pipe test 4 PMI TI PHY interrupt test 5 Frame read write test 6 Adapter check test 0x7c 0x14...

Page 55: ...ddress 0x88 Ethernet address 0x86 Ethernet address 0x89 0xff Checksum 0x8a 0xff Checksum 0x8b 0x83 0x8c 0x08 0x8d 0x00 0x8e Token ring address 0x8f Token ring address 0x90 Token ring address 0x91 Token ring address 0x92 Token ring address 0x93 Token ring address 0x94 0xff Checksum 0x95 0xff Checksum 0x96 0x82 0x97 0x08 0x98 0x00 0x99 Ethernet address 0x9a Ethernet address 0x9b Ethernet address ...

Page 56: ...0xa0 0xff Checksum 0xa1 0x83 0xa2 0x08 0xa3 0x00 0xa4 Token ring address 0xa5 Token ring address 0xa6 Token ring address 0xa7 Token ring address 0xa8 Token ring address 0xa9 Token ring address 0xaa 0xff Checksum 0xab 0xff Checksum 0xac 0x82 0xad 0x08 0xae 0x00 0xaf Ethernet address 0xb0 Ethernet address 0xb1 Ethernet address 0xb2 Ethernet address 0xb3 Ethernet address 0xb4 Ethernet address 0xb5 0x...

Page 57: ...ddress Description Binary Bits Default 0xb6 0xff Checksum 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 Vendor ID register LSbyte 0xc1 Vendor ID MSbyte 0xc2 Device ID LSbyte 0xc3 Device ID MSbyte 0xc4 Revision 0xc5 Subclass 0xc6 Min_Gnt 0xc7 Max_Lat 0xc8 Checksum ...

Page 58: ...ransmit and receive frames It provides examples of the necessary code beginning with configuration of the ThunderLAN device on a peripheral com ponent interconnect PCI system The chapter also defines the steps needed for both hardware and software reset Topic Page 3 1 Initializing 3 2 3 2 Resetting 3 8 Chapter 3 ...

Page 59: ...hunderLAN device ID and should also have a vendor ID The example code uses the TI vendor ID The call to find the board is define TLAN_DEVICEID 0x0500 PCI TLAN device ID define TI_VENDORID 0x104C PCI vendor ID assigned to TI if PciFindDevice TLAN_DEVICEID TI_VENDORID 0 nic DevId error The PCI Bios can t find a TLAN board PciFindDevice is further broken down to an O S call to the PCI interrupt servi...

Page 60: ... int r h ah When the BIOS call is finished the value returned is 0 if successful or an error code if not successful Once the BIOS board is found references to it and prop erties assigned to it by the O S are indirectly referenced by the value returned to nic devid The structure nic is a collection of properties belonging to the NIC As the sample code learns more about the environment with respect ...

Page 61: ... checked If an I O base register is found it is stored away in the structure nic If neither of the first two locations is a valid I O base register an error is declared and the program is ended Note that the configuration space was originally supplied with a space request and the operating system as part of the power on self test POST supplied the card with sufficient address space by filling in t...

Page 62: ...t this piece of information is retrieved via the key parameter of the evalua tion module network interface card s EVMNIC s PCI devIce ID define PCI_INTLINE 0x3C if nic Irq PciRdByte nic DevId PCI_INTLINE error PCI Config failed Unconfigured interrupt Implemented hardware interrupts in a PC range from 0 to 15 but 0 is usually unavailable to peripherals It is suggested that a value of 0 or greater t...

Page 63: ... Where these constants have the following values define PCI_COMMAND 0x04 define IO_EN 0x0001 define MEM_EN 0x0002 define BM_EN 0x0004 and PciWrWord a register level int86 O S call has the following definition void PciWrWord WORD devid WORD addr WORD data The PciWrWord statement goes to the PCI configuration space associated with the evaluation module EVM device ID and writes to the PCI command reg...

Page 64: ... arrangement the driver can find the silicon revision and the board revision nic Rev DioRdByte nic IoBase NET_DEFREV define NET_DEFREV 0x0C default revision reg DioRdByte calls a routine that loads the host DIO_ADR register with NET_DEFREV and does a byte enabled read of the host DIO_DATA register returning the value to the member rev value of DIO_DATA for structure nic 3 1 6 Setting the PCI Bus L...

Page 65: ...the FXTL1 and FXTL2 lines 1 Sync all attached PHYs 2 Isolate all attached PHYs by writing the PDOWN LOOPBK and ISOLATE bits into the control register the GENen_ctl register in ThunderLAN 3 Enable the internal PHY by writing 0x4000h LOOPBK in the GENen_ctl register 4 Wait 500 ms for the crystal frequency to stabilize 5 Reset the PHY state machine by asserting the LOOPBK and RESET bits in the GENen_...

Page 66: ...T_CMD register 3 Disable interrupts by asserting the Ints_off bit in HOST_CMD 4 Setup the Areg and HASH registers for Rx address recognition 5 Setup the NetConfig register for the appropriate options 6 Setup the BSIZEreg register for the correct burst size 7 Setup the correct Tx commit level in the Acommit register 8 Load the appropriate interrupt pacing timer in Ld_Tmr in HOST_CMD 9 Load the appr...

Page 67: ...3 10 ...

Page 68: ...ecognizes prioritizes and acknowl edges these interrupts It defines specific interrupt codes and describes what happens when these occur This allows the user to diagnose and correct any conditions which may cause failure Topic Page 4 1 Loading and Unloading an Interrupt Service Routine ISR 4 2 4 2 Prioritizing Adapter Interrupts 4 5 4 3 Acknowledging Interrupts Acking 4 6 4 4 Interrupt Type Codes ...

Page 69: ...erations that can hang the PC and can also provide time stamp information for operations nic OldTimer HwSetIntVector BYTE 0x1C TimerIsr The driver points to the next code to execute when the timer interrupt goes off and saves the value for program restart nic OldTimer is a storage place for this information reserved in a routine called NICEVN which is allocated for each NIC this instance is called...

Page 70: ...nic OldTimer If a time out value has been set nic OldTimer is decremented If it reaches 0 it sets an internal program flag that is checked in the main program loop If the OldTimer value is not 0 there was a vector saved in this NIC s instance of the structure NICEVN the routine branches to that code so that whatever else needs to be done on the PC on a timer tick is done The next interrupt service...

Page 71: ...c OldTimer if nic OldAbort HwSetIntVector 0x23 nic OldAbort The next interrupt to be intercepted corresponds to the actual hardware inter rupt Since the original installation for a ThunderLAN controller is a PCI slot its interrupt in the PC is assigned by the PCI BIOS code You must interrogate the PCI configuration space to find it This was done in the previous section as part of GetPciConfig It u...

Page 72: ...lowing order Adapter check interrupts cause an internal ThunderLAN reset clearing all other interrupt sources Adapter check interrupts can only be cleared by a PCI hardware PRST or software Ad_Rst reset Network status interrupts Statistics interrupts List interrupts which service transmit and receive interrupts in a round robin fashion J Receive end of frame EOF interrupts have higher priority tha...

Page 73: ...rupts can be disabled by writing to the HOST_INT register One quick and easy way of doing this is by writing the contents of HOST_INT back after read ing it at the start of the interrupt routine A jump table contains the starting address of the individual interrupt routines Offsets to this table can be easily created from the HOST_INT vector read It may be necessary to shift the vector read in ord...

Page 74: ...n to it by the Ack_Count register In this way the host is able to acknowledge mul tiple Tx EOFs in a single interrupt call The host must count the number of frames it has transmitted by counting the frames with the Frm_Cmp bit set in the CSTAT field and must use this number in the Ack_Count field while ac knowledging A special case of this first option is when the interrupt threshold is set to a v...

Page 75: ...is time there is no Rx interrupt threshold so each frame immedi ately triggers an interrupt On receiving an Rx EOF the driver Reads the Data_Address and Data_Count pointers Determines how many bytes to copy to the Rx buffer or whether there is a buffer into which a frame can be copied Copies data into the Rx buffer pointed to by the fragments Data_Count Data_Address field pairs Passes control of t...

Page 76: ...erface PHY with enhanced media indepen dent interface MII support is used Some other causes of a status interrupt occur when the Tx and Rx channels are stopped using a STOP command The following shows the flow for a status interrupt routine Reads the NetSts register Clears the NetSts register NetSts can be easily cleared by writing what has been read back into it Reads the NetMask register Uses Ne...

Page 77: ... interrupts Reads the adapter check code from the CH_PARM register Clears any Tx queued transmissions In an adapter check ThunderLAN is not on the network wire Reads the statistics registers since these are lost when ThunderLAN is reset Performs a software reset by asserting the Ad_Rst bit in the HOST_CMD register Exits the routine but does not acknowledge since reset clears the interrupt The adap...

Page 78: ...his bit is set to 0 a PCI data transfer operation was in progress at the time of the failure 19 R T Receive not transmit If this bit is set to 1 a PCI receive channel operation was in prog ress at the time of the failure If this bit is set to 0 a PCI transmit channel operation was in progress at the time of the failure 18 R W Read not write If this bit is set to 1 a PCI read operation was in progr...

Page 79: ...ue to a target abort 05h ListErr List error The sum of a transmit list s data count fields was not equal to the frame length indi cated in the list s frame size field The last nonzero fragment of a receive or transmit list did not have bit 31 of the data count field set Please note that if you are in multifragment mode and are using less than ten frag ments the fragment after the last fragment use...

Page 80: ...s in the lists where the frame size given to ThunderLAN does not match the actual frame size They also include instances where the driver and ThunderLAN do not agree on how many EOFs to acknowledge This is a serious mistake since it means that frames have been lost These adapter checks show faults in the driver hardware interaction that must be resolved 4 4 9 Rx EOC Interrupt Int_type 111b A Rx EO...

Page 81: ...4 14 ...

Page 82: ...e data to be transmitted or where the receive buffer is located This chapter discusses the advantages of using a system of linked list structures to support continuous network transmission and recep tion It also discusses list format and how to effectively manage this system of linked lists by the use of interrupts Topic Page 5 1 List Management 5 2 5 2 CSTAT Field Bit Requirements 5 5 5 3 One Fra...

Page 83: ... may not hold more than one frame A list may point to one or more buffers for the frame associated with those buffers Frame A frame is the data that is transmitted on the network A frame can use one or multiple buffers GO Command A GO command tells ThunderLAN to initiate frame transmission or re ception ThunderLAN uses the list structure to determine which buff ers to use in this process Ack Ackin...

Page 84: ...agement technique where the pointers are relinked sequentially The lists are linked by pointing the for ward pointer in the previous list to the address of the next list The first list structure is shown on the left where list 1 s forward pointer points to the physical address of list 2 and list 2 s forward pointer points to the physi cal address of list 3 List 3 has a forward pointer equal to 0x0...

Page 85: ...r copying the list header and servic ing the interrupts and the list If the copy time does not meet this criterion it may be necessary to add an additional Rx list and buffer to your driver application An efficient driver actually takes up significantly less memory space than a less efficient driver and it is able to use more network bandwidth and less CPU This is because a more efficient driver u...

Page 86: ...esponds to bit 3 in the TI380 CSTAT FRAME_END bit Bit 13 in ThunderLAN corresponds to bit 2 in the TI380 CSTAT FRAME_START bit We define bits 12 and 13 as 1 since that is the way that they would appear on TI380 drivers where one list handles one frame only ThunderLAN was designed so that a TI380 driver could be easily modified to become a ThunderLAN driver Texas Instruments has reserved the use of...

Page 87: ...g ments on that list In the case of a receive list the driver has the option to force ThunderLAN to DMA a one fragment list This is accomplished by setting the One_Frag bit in the NetConfig register to 1 In one fragment mode ThunderLAN only needs to DMA a 16 byte list instead of an 88 byte list This helps to cut down on PCI bandwidth use Currently there is no one fragment mode for transmit ...

Page 88: ...Data count Data address Data address Data count Data count Data address Data address Data count Data address Data address Data count Receive CSTAT Frame size Forward pointer Byte 0 Byte 1 Byte 2 Byte 3 Note All receive lists must start on an eight byte address boundary Figure 5 4 Receive List Format One_Frag 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ...

Page 89: ...o report frame completion status When initially written to by the host this field is referred to as the receive CSTAT request field After a frame finishes receiving the adapter overwrites this field and it is referred to as the receive CSTAT complete field This indicates completion of frame reception not completion of the receive command The bit definitions for these two fields are contained in la...

Page 90: ...Bits Bit Name Function 15 0 Ignored by adapter Set to 0 14 Frm_Cmp 0 Frame complete Ignored by adapter Set to 0 Setting the Frm_Cmp bit to 0 is good programming practice 13 1 Ignored by adapter Set to 1 12 1 Ignored by adapter Set to 1 11 0 Ignored by adapter Set to 0 10 0 Ignored by adapter Set to 0 9 0 Ignored by adapter Set to 0 8 0 Ignored by adapter Set to 0 7 0 0 Ignored by adapter Set to 0 ...

Page 91: ...register no interrupts will be generated This bit will serve as an indication of RX EOC in that case This bit will also be set when interrupts are enabled 10 Rx_Error Error frame Frames with CRC alignment or coding errors are passed to the host if the CAF Copy All Frames and PEF Pass Error Frames option bits are set Such frames can be identified through the Rx_Error bit These frames have this bit ...

Page 92: ...ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ List offset 0x54 0x50 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Data count Data address Data count Data count Data address Data address Data count Data address Data count Data count Data address Data ad...

Page 93: ... frame This field must be equal to the sum of the data count fields or an adapter check occurs Transmit CSTAT This 16 bit parameter is written by the host when the transmit parameter list is created It is overwritten by the adapter to report frame transfer status When initially written by the host this field is referred to as the transmit CSTAT request field After a frame is transferred into the a...

Page 94: ...RC Pass CRC When this bit is set to a 1 the adapter uses the last four bytes of frame data as the frames CRC The integrity of this CRC is not checked and it is handled just like the data payload If this bit is set to a 0 CRC is generated by the adapter as normal 8 0 Ignored by adapter Should be set to 0 7 3 Reserved This field is Ignored by the adapter but should be set to 0 2 0 Network priority N...

Page 95: ... host in CSTAT request field 12 1 Same value as previously set by the host in CSTAT request field 11 TX EOC TX EOC If TX EOC is disabled by the Interrupt Disable register no interrupts will be generated This bit will serve as an indication of TX EOC in that case This bit will also be set when interrupts are enabled 10 0 Same value as previously set by the host in CSTAT request field 9 Pass_CRC Sam...

Page 96: ...erLAN Frames are units of data that are transmitted on a network These must appear in a consistent logical format to be recognized The chapter also describes the method you must use to create a linked list structure which is necessary to start frame reception and transmission Topic Page 6 1 Frame Format 6 2 6 2 GO Command 6 4 Chapter 6 ...

Page 97: ... on the network The ThunderLAN adapter allows received frame data to be frag mented into up to ten pieces However the adapter provides the data in a con sistent logical format as shown below This logical format is different for token ring and Ethernet frame formats Figure 6 1 Token Ring Logical Frame Format Rx 18 bytes max 6 bytes 6 bytes 1 byte 1 byte Data Routing field optional Source address De...

Page 98: ...expects the conca tenation of these fragments to be in a consistent logical format as shown be low This logical format is different for token ring and Ethernet frame formats Figure 6 3 Token Ring Logical Frame Format Tx 18 bytes max 6 bytes 6 bytes 1 byte 1 byte Data Routing field optional Source address Destination address FC AC Figure 6 4 Ethernet Logical Frame Format Tx 3 to 4 bytes 2 bytes 6 b...

Page 99: ...e field d Sets the data count to the length of the receive buffer This is a flag that tells ThunderLAN that it is the last fragment e Calculates the list s receive buffer s physical address and writes it to the data address 4 Sets up the next list After all lists are complete ThunderLAN goes to the last list s forward pointer and sets it to 0x00000000h To begin frame reception the host 1 Creates a...

Page 100: ...eive buffer to place frames in and the receive channel remains open If ThunderLAN encounters the 0 forward pointer meaning that it has filled the last buffer available to it it gives the host an Rx EOC interrupt and stops the receive channel Implementing continuous receive reduces the possibility of losing frames due to not having receive buffers In continuous receive the driver acknowledges Rx EO...

Page 101: ...for this list by setting bits 12 and 13 to 1 c Initializes the frame_size to the transmit frame s size d Sets the data count to 0x80000000h This is a flag that tells Thunder LAN that it is the last fragment ThunderLAN however DMAs the en tire ten fragments even though it may only use one fragment e Calculates the list s transmit buffer s physical address and writes it to the data address 4 Sets th...

Page 102: ... the Frm_Cmp bit in the CSTAT field ThunderLAN sets the bit when the frame is transmitted to the FIFO not when network transmission is complete The driv er looks into the Frm_Cmp bit to verify frame transfer Depending on the value loaded into the Ld_Thr bit in HOST_CMD a Tx EOF interrupt is given to the host The driver then needs to acknowledge the number of frames it has sent to ThunderLAN This i...

Page 103: ...al transmit FIFO and subsequently to the network There are two steps involved in issuing a Tx GO command 1 In the CH_PARM register write the physical address of the beginning of the list structure ThunderLAN uses this physical address to DMA data from host memory 2 In the HOST_CMD register write the appropriate bits to start the channel The Tx GO command writes to the GO bit and selects the transm...

Page 104: ...as Instruments TNETE211 100VG AnyLAN physical media independent PMI device The TNETE211 implements 802 12 media access controller MAC state machines for 100VG AnyLAN operation and provides an 802 12 compatible MII In addition interrupt driven PHYs can be implemented through the use of the enhanced MII ThunderLAN can use nonmanaged no serial management in terface MII devices ThunderLAN also support...

Page 105: ...software into a mode that supports a connection to the TNETE211 The TNETE211 device provides full 802 12 functionality and a 802 12 MII which allows connection to a PHY for 100VG AnyLAN The MII mode can be selected using the MAC_Select field in the NetConfig register Figure 7 1 100VG AnyLAN Support Through ThunderLAN s Enhanced 802 3u MII 802 12 MII TNETE211 PCI MII TLAN TLAN 802 3u MII PCI Thunde...

Page 106: ...MRCLK In Receive clock Receive clock source from the attached PHY MRXD0 MRXD1 MRXD2 MRXD3 In Receive data Nibble receive data from the PHY Data on these pins is always synchronous to MRCLK MRXDV In Receive data valid Indicates data on MRXD 3 0 is valid MRXER In Receive error Indicates reception of a coding error on received data MDCLK Out Management data clock Serial management interface to PHY ch...

Page 107: ...nderLAN architecture supports is the ability to be interrupted by the PHY This is accomplished through Thunder LAN s enhanced MII The MII enhanced interface allows the PHY to interrupt the host system to indicate that the PHY needs some type of service rather than requiring the host to constantly poll the MII registers The interrupt mechanism described here is an extension of the 802 3u stan dard ...

Page 108: ...f way point These counters should clear when read This ac tion also disables the counter event function The design of the interrupt generating logic in the PHY should minimize the number of interrupts generated so that overall system performance is not im pacted To achieve this the events that cause an interrupt are detected by change and not by absolute value The host when interrupted reads the P...

Page 109: ...T QCYC Quiescent Since the Interrupt from the PHY is an open drain function the PMI drives the MDIO low prior to the falling edge that starts the start of frame SOF portion of the management interface frame During sync cycles the PHY releases the interrupt on the MDIO to allow the management entity to pull the MDIO high so a sync cycle is seen In the diagram below only one sync cycle is displayed ...

Page 110: ...cal Interface PHY 7 2 Nonmanaged MII Devices Nonmanaged MII devices do not have a management interface MDIO and MDCLK As such they do not have any registers The driver must have a key word that denotes that the PHY used is nonmanaged ...

Page 111: ...e is MRXD0 RXD receive data MRCLK RXC receive clock MRCLK RXC receive clock MCRS CRS carrier sense MTCLK TXC transmit clock MTXD0 TXD transmit data MTXEN TXE transmit enable MCOL COL collision detect MTXD3 MTXD2 MTXD1 and MTXER are driven with the values in the low nibble bits 0 3 of the Acommit register These signals can be used to drive PHY option pins such as loopback or unshielded twisted pair...

Page 112: ...N_ctl The effect of asserting the isolate bit in this register is that the PHY does not drive any wire port or magnetics it is connected to and it Hi Zs the interface to the MII data bus The PHY still pays attention and responds to requests from the MII management interface consisting of the MDIO MDCLK lines Nominal treatment of the attached PHY requires 32 clock cycles be applied to the PHY to sy...

Page 113: ...7 10 ...

Page 114: ...reg isters to store information on its internal status and its communication with the host This appendix describes the purpose and function of each register and provides bitmaps and descriptions of individual bits Topic Page A 1 PCI Configuration Registers A 2 A 2 Adapter Host Registers A 12 A 3 Adapter Internal Registers A 21 A 4 10Base T PHY Registers A 39 Appendix A ...

Page 115: ...as a classical chip select signal indi cating there are configuration accesses to this device Special configuration read or write cycles are used for the accesses and individual registers are ad dressed using AD 7 2 and PCI bus byte enables The adapter only implements mandatory or applicable configuration registers in the standard PCI header region No adapter specific configuration registers are d...

Page 116: ...h Reserved 00h PCI NVRAM Reserved 00h Reserved 00h IntDis 28h read only 48h B4h read only Reserved 00h A 1 1 PCI Autoconfiguration from External 24C02 Serial EEPROM ThunderLAN allows some of the PCI configuration space registers to be loaded from an external serial EEPROM These registers contain fixed vendor and device information Autoconfiguration allows builders of ThunderLAN sys tems to customi...

Page 117: ... to the adapter s configuration space during autoload are re jected with a target retry The checksum byte is an 8 bit cumulative XOR of the eight shaded bytes starting with an initial value of AAh The adapter uses this checksum to validate the EEPROM data If the checksum fails the config uration registers are set to their default hardwired values instead Checksum AAh XOR Data 0 XOR Data 1 XOR Data...

Page 118: ...are ignored bit is always read as 0 6 PAR_En Parity enable Enables the adapter PCI parity checking A value of 1 allows the adapter to check PCI parity a value of 0 causes PCI parity errors to be ignored 5 3 Reserved Writes to these bits are ignored bits are always read as 0 2 BM_En Bus master enable Enables the adapter as a PCI bus master A value of 1 enables bus master operations a value of 0 dis...

Page 119: ...nd only be cleared by the host s writing a 1 to this bit position 12 RT_ab Received target abort When set indicates a ThunderLAN master cycle was aborted due to a target abort This bit can only be set by the adapter and only be cleared by the host s writing a 1 to this bit position 11 Reserved 10 9 Devsel PDevSel timing These bits indicate the PDEVSEL timing supported by ThunderLAN These bits are ...

Page 120: ... is loaded with 0x20h to indicate pattern generation 2 0 PG 2 0 ThunderLAN A 1 10 PCI Cache Line Size Register 0Ch This register informs the adapter of the memory system cache line size This is used to determine the type of memory command used by ThunderLAN in PCI bus master reads Memory read line is used for data reads of less than four cache lines Memory read multiple is used for data reads of f...

Page 121: ...n 32 bit address space Bit 3 of this register prefetchable bit is hardwired to a 0 indicating that prefetching is not allowed A 1 14 PCI BIOS ROM Base Address Register 30h Reserved 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BIOS ROM Base Address 16 MSBs BRE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 This register holds the base address for ThunderLAN s BIOS ROM in memory space Bit 0 BRE is an enab...

Page 122: ...e ignored 2 Reserved This bit is always be read as 0 Writes to this bit are ignored 1 CDIR Clock direction When set to a 1 the EDCLK pin is driven with the value of the CLOCK bit When set to a 0 EDCLK pin is not driven and the value read from the CLOCK bit reflects the incoming value on the EDCLK pin 0 CLOCK Clock bit This bit is used to read or write the state of the EDCLK pin When CDIR is set to...

Page 123: ... bus PRST line during soft Ctrl Alt Del resets but still performs diagnostics on PCI bus de vices The automatic software reset feature ensures the adapter is reset and therefore not performing PCI bus master operations before diagnostics are started Soft resets are detected as the deassertion of the BM_En Mem_En and IO_En bits in the PCI command register This differentiates soft resets from bus ma...

Page 124: ... this register is hardwired to a value of 10000107h which indicates that the CIS information is in expansion ROM at image1 and offset 20 For a detailed explanation of the CIS Pointer refer to the 1995 PC Card Stan dard Electrical Specification The subject is covered under the heading CIS Pointer and describes the types of information provided and the organization of this information 0 Address Spac...

Page 125: ...ck Stop Go Byte 0 Byte 1 Byte 2 Byte 3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A 5 Host_CMD Register Bits Bit Name Function 31 Go Channel go This command bit only affects the network channels if R T 0 Tx GO Writing a 1 to this bit starts frame transmission on a stopped or inactive channel Ch_Parm contains the address of the first transmit list if...

Page 126: ... placed in a reset state as soon as any ongoing PCI bus transfers are complete end of current data fragment list or CSTAT DMA The RXSTOP3 bit in the NetSts register is set to indicate that the receiver has been halted While the receiver is stopped no network Rx statistics are gathered as the Rx state machines are in reset If a STOP is requested during the completion of the DMA of a transfer frame ...

Page 127: ...ttempt is made to ac knowledge more EOFs than the adapter has outstanding an AckErr adapter check is raised if Nes 1 EOC 0 and R T 1 Rx EOF Ack Writing a 1 to this bit acknowledges and clears 1 or more Rx EOF interrupts for the chan nel indicated in Ch_Sel as indicated in the Ack Count field If an attempt is made to ac knowledge more EOFs than the adapter has outstanding an AckErr adapter check is...

Page 128: ... command bits and allows a command to be issued in a single write cycle 18 Nes Not error statistics This read write bit is used to select between status error statistics operations and channel operations If this bit is set to a 0 then status statistics opera tions are selected If set to a 1 channel operations are selected This field can be written in the same cycle as the command bits and allows a...

Page 129: ...fect This bit is always read as 0 11 Ints_off Turn PCI interrupts off Writing a 1 to this bit disables ThunderLAN interrupts to the host PINTA will never be asserted Writing a 0 to this bit has no effect This bit is always read as 0 10 Ints_on Turn PCI interrupts on Writing a 1 to this bit reenables ThunderLAN interrupts after an Ints_off command bit write Writing a 0 to this bit has no effect Thi...

Page 130: ...ee LSBs must be 0 Load CH_PARM and write the GO bit with no intervening DIO accesses as the DIO_DATA and CH_PARM registers share a common holding register Driver writers must ensure that the code that loads CH_PARM and writes the GO bit is noninterruptable Otherwise an intervening DIO could occur corrupting the list address and resulting in unpredictable operation When read the LSB of the CH_PARM ...

Page 131: ...this is a network status interrupt If Int_Vec is not 0 this is an adapter check interrupt 111 Rx EOC This field is read only but writing a nonzero value to it causes the adapter PCI interrupt to be disabled deasserted until after a 1 is written to the Ack command bit in HOST_CMD If this register is not written to it maintains the highest priority interrupt that is available even if the driver is c...

Page 132: ...s set to 1 DIO accesses are to the muxed SRAM If this bit is set to 0 DIO accesses are to internal ThunderLAN registers The internal muxed SRAM can only be accessed while the adapter is in reset NRESET bit in the NetCmd register is set to a 0 Accesses to the SRAM while the adapter is not in reset are undefined they are ignored and return unknown data 13 0 ADR_SEL This field contains the DIO addres...

Page 133: ... no actual DIO_DATA register ac cesses to this address are mapped to an internal bus access at the address specified in the DIO_ADR register The DIO_DATA location uses 32 bit PCI data transfers with full byte control following the normal PCI Local Bus Specification conventions ThunderLAN uses the target ready PTRDY signal to insert PCI wait states and to ensure correct data transfers Writes to thi...

Page 134: ...us byte enables are maintained on this internal bus allowing arbitrary byte transfers DIO accesses are primarily used to initialize and control the ThunderLAN con troller Normally only ThunderLAN controller registers are accessible by DIO In adapter test mode PCI configuration option the SRAM FIFO control regis ters and some PCI controller registers are also accessible The content and meaning of s...

Page 135: ..._1 39 to 32 Areg_1 47 to 40 Areg_0 7 to 0 Areg_0 15 to 8 0x14 Areg_1 7 to 0 Areg_1 15 to 8 Areg_1 23 to 16 Areg_1 31 to 24 0x18 Areg_2 23 to 16 Areg_2 31 to 24 Areg_2 39 to 32 Areg_2 47 to 40 0x1C Areg_3 39 to 32 Areg_3 47 to 40 Areg_2 7 to 0 Areg_2 15 to 8 0x20 Areg_3 7 to 0 Areg_3 15 to 8 Areg_3 23 to 16 Areg_3 31 to 24 0x24 HASH2 0x28 HASH1 0x2C Tx underrun Good Tx frames 0x30 Rx overrun Good R...

Page 136: ...pends on the MAC pro tocol in use CSMA CD mode If this bit is set the receiver does not discard frames that are shorter than a slottime 64 bytes Demand priority token ring mode This bit has no function 4 CAF Copy all frames When this bit is set to 1 the ThunderLAN controller receives frames indiscriminantly without regard to destination address CAF does not copy error frames unless the PEF bit in ...

Page 137: ...tten to the NetSio register takes control of the EEPROM interface pins On reset software or hardware control of the inter face is given to the PCI NVRAM register All bits in this register are set to 0 on an Ad_Rst or when PRST is asserted 8 9 10 11 12 13 14 15 MDATA MTXEN MCLK NMRST EDATA ETXEN ECLOK MINTEN Byte 1 Table A 9 Network Serial I O Register Bits Bit Name Function 15 MINTEN MII Interrupt...

Page 138: ...riven with the value in the MDATA bit When this bit is set to 0 the MDATA bit is loaded with the value on the MDIO pin 8 MDATA MII SIO data This bit is used to read or write the state of the MDIO pin When MTXEN is set to 1 MDIO is driven with the value in this bit When MTXEN is set to 0 this bit is loaded with the value on the MDIO pin A 3 3 Network Status Register NetSts 0x00 DIO All bits in this...

Page 139: ...responding status flag is set All bits in this register are set to 0 on an Ad_Rst or when PRST is asserted 24 25 26 27 28 29 30 31 Reserved MASK4 MASK5 MASK6 MASK7 Byte 3 Table A 11 Network Status Mask Register Bits Bit Name Function 31 MASK7 MII interrupt mask When this bit is set a network status interrupt is posted if the MIRQ bit in the NetSts register is set 30 MASK6 Heartbeat error mask When...

Page 140: ...ng the bit has been cleared 14 Tclk test Test MTCLK This test sense bit allows the host to verify presence of a clock on the MTCLK pin This bit can only be written as a 1 Writing a 0 to this bit has no effect This bit is cleared to 0 by a rising edge on MTCLK Host software verifies a minimum clock frequency by setting this bit waiting for the maximum clock period and then verifying the bit has bee...

Page 141: ...umber of PCI cycles needed to read the receive list 9 One chn One channel mode When this bit is set to 1 the adapter only supports a single transmit channel rather than two When this bit is set to 0 the adapter supports two transmit channels The adapter has 3K bytes of FIFO RAM for frame buffering In normal two channel mode 1 5K is allocated to Rx one Rx channel and 1 5K to transmit 0 75K per Tx c...

Page 142: ...gister ManTest 0x04 DIO This 16 bit register is used for manufacturing test The options controlled by this register only take effect while the MTEST bit in the NetConfig register is set The functions controlled by this register are for Texas Instruments manufacturing test only A 3 7 Default PCI Parameter Registers 0x08 0x0C DIO These eight read only bytes indicate the default contents of the autol...

Page 143: ... register for address comparison while being written or when it is uninitialized Addressing lockout is enabled at NRESET or whenever the first Areg 47 40 register byte is written and it is disabled whenever the last Areg 7 0 register byte is written A 3 8 1 The All Nodes Broadcast Address In addition to the general address matching of specific or group addresses the adapter also responds to the al...

Page 144: ... data value from the 48 bit destination address as follows Hash_fun 0 DA 0 xor DA 6 xor DA 12 xor DA 18 xor DA 24 xor DA 30 xor DA 36 xor DA 42 Hash_fun 1 DA 1 xor DA 7 xor DA 13 xor DA 19 xor DA 25 xor DA 31 xor DA 37 xor DA 43 Hash_fun 2 DA 2 xor DA 8 m xor DA 14 xor DA 20 xor DA 26 xor DA 32 xor DA 38 xor DA 44 Hash_fun 3 DA 3 xor DA 9 xor DA 15 xor DA 21 xor DA 27 xor DA 33 xor DA 39 xor DA 45...

Page 145: ...e lost even when registers are read a byte at a time Writing to a statis tics register has no effect The MSBs of all the error counters are ORed together to create the statistics overflow interrupt vector Int_type 010 in the HOST_INT register As more than one counter may have overflowed all statistics registers must be read cleared on a statistics overflow interrupt Figure A 6 Ethernet Error Count...

Page 146: ...t without alignment or coding errors This is a byte wide counter Code error frames are received with alignment not an even number of nibbles or code errors MRXER signaled from PHY This is a byte wide counter Multicollision Tx frames have encountered 2 to 15 collisions before being transmitted on the network This is a 16 bit counter Single collision frames have encountered one collision before bein...

Page 147: ...us latencies This is a byte wide counter Good Rx frames are received without errors This is a 24 bit counter Good frames are received more frequently than errored frames Rx overrun frames are address matched and could not be received due to inadequate resources Rx FIFO full This is a byte wide counter CRC error frames are received with CRC errors but without alignment or coding errors This is a by...

Page 148: ...ken by detecting this condition and allowing network transmission to proceed before the full commit level is reached This situation only occurs where large commit levels are combined with large fragment burst and frame sizes 27 24 PHY options When ThunderLAN is configured for a bit rate CSMA CD MII BITrate option bit in the NetConfig register the contents of these bits are presented on the MTXD 3 ...

Page 149: ...erations Tx list or data transfers The code indicates the maximum num ber of bytes to be transferred in any one transmit DMA data burst At reset the burst size is set to a default level of 64 bytes code 2 The burst size codes are 0 16 bytes 1 32 bytes 2 64 bytes default 3 128 bytes 4 256 bytes 5 7 512 bytes 8 F reserved 11 8 Rx burst size Receive burst size This nibble code indicates the burst siz...

Page 150: ... result in frames not being co pied and an Rx overrun The register holds the maximum frame size in bytes The value in the register indicates the maximum frame size that can be accommodated in the host buff ers Frames larger than this value are discarded except in PEF mode A value of 0 in this register default is equivalent to a maximum frame size of 64K by tes the adapter attempts to receive all f...

Page 151: ...iority Error Counters Bit Name Function 7 3 Reserved 2 TX EOC Disable Transmit End of Channel Select When this bit is set to 1 all transmit channels of TX EOC interrupts are disabled Default value is 0 1 RX EOF Disable Receive End of Frame Select When this bit is set to 1 RX EOF interrupts are disabled Default value is 0 0 RX EOC Disable Receive End of Channel Select When this bit is set to 1 the ...

Page 152: ...f which are hardwired The diagram be low shows the devices register map The registers shown in gray are the ge neric registers mandated by the MII specification The registers shown in white are TI specific registers Figure A 8 10Base T PHY Registers GEN_id_lo GEN_id_hi GEN_sts GEN_ctl Reserved Reserved Reserved AN expansion AN link partner ability AN advertisement TLPHY_sts TLPHY_ctl TLPHY_id Thun...

Page 153: ...tion process If this bit is clear the link shall be configured via the DUPLEX bit and the PHY will implement the standard 10Base T link integrity test The default value of this bit is enabled If this bit is set to one the PHY engages in autonegotiation when a link fail condition is detected The link will not be valid until the AUTOCMPLT bit is set to one The PHY does not automatically configure it...

Page 154: ...AUTORSRT Restart autonegotiation The autonegotiation process is restarted by setting this bit to 1 This bit is self clearing and the PHY returns a value of 1 in this bit until the autonegoti ation process is initiated 8 DUPLEX Duplex mode Setting this bit to a 1 configures the PHY for full duplex 10Base T opera tion whereas setting this bit to 0 default configures the PHY for half duplex operation...

Page 155: ..._exp are valid This bit is 0 only during an actual negotiation process 4 RFLT Remote fault This bit mirrors the LPRFLT bit received in the most recent autonegotiation link code word When set to 1 this bit indicates that the link partner is in a fault condition 3 1 Autonegotiation ability The PHY supports autonegotiation 2 LINK Link status When this bit is read as 1 it indicates that the PHY has de...

Page 156: ...if the AUI interface is selected The jabber condition occurs when a single packet transmission exceeds 20 ms this cannot happen through normal TLAN operation In the jabber condition all transmit re quests are ignored and collision detection is disabled as is the internal loopback of transmit data when in half duplex mode The jabber condition persists for 28 576 ms after the deassertion of the MTXE...

Page 157: ...nizationally unique identifier OUI Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 These two hardwired 16 bit registers contain an identifier code for the TLAN 10Base T PHY GEN_id_hi contains 0x4000 GEN_id_lo contains 0x50xx where the xx denotes the revision The revision number value xx has changed from 14 to 15 for the GEN_id_lo register ...

Page 158: ...on process 13 TLRFLT TLAN remote fault This bit enables TLAN to indicate a remote fault condition to the link partner 12 5 Technology ability field Autonegotiation advertised technology ability This 8 bit value is sent to the link partner to indicate the abilities of the TLAN PHY Unsupported abilities cannot be advertised which for this PHY means only two bits have meaning when set Bit 6 PHY suppo...

Page 159: ...he autonegotiation process 13 LPRFLT Link partner remote fault When this bit is set to a 1 the link partner reports a remote fault condition 12 10 Reserved For future IEEE defined abilities 9 100Base T4 Set to 1 if supported by the link partner 8 100Base Tx full duplex Set to 1 if supported by the link partner 7 100Base Tx Set to 1 if supported by the link partner 6 10Base T full duplex Set to 1 i...

Page 160: ...ge able When this bit is set to 1 the link partner indicates that it implements autonegotiation next page abilities 2 0 Next page able ThunderLAN does not support next page transmission or reception 1 PAGERX Page received This bit is set after three identical and consecutive link code words have been received from the link partner and the link partner has indicated that it has received three ident...

Page 161: ...hardwired 16 bit register contains a TI assigned identifier code for the ThunderLAN PHY PMIs An additional identifier is required to identify non 802 3 PHY PMIs which are not otherwise supported by the 802 3u MII specification The identifier code for the internal 10Base T AUI PHY is 0x0001 ...

Page 162: ...ivers on the PHY are multiplexed between AUI and 10Base T so both cannot operate simultaneously 12 SQEEN SQE signal quality error enable Writing a 1 to this bit causes the 10Base T PHY to perform the SQE test function at the end of packet transmission The SQE function is only performed in 10Base T mode The SQE test provides an internal simulated collision to test the collision detect circuitry It ...

Page 163: ...15 Table A 25 ThunderLAN PHY Status Register Bits Bit Name Function 15 MINT MII interrupt This bit indicates an MII interrupt condition The MII interrupt request is activated and latched until the register is read Writing to this bit has no effect This bit is set to a 1 when PHOK is set to 1 LINK changes state or is different from either the last read value or the current state of the link RFLT is...

Page 164: ...ses has been detected 12 TPENERGY Twisted pair energy detect This bit only has meaning in AUI mode When set to a 1 it indicates that the PHY receives of impulses on the FRCVP FRCVN pins Energy is de tected in the form of link pulses the sense of which is determined by the POLREV bit Note that if the POLREV bit is set incorrectly link pulses are not seen and this bit is not set 11 0 Reserved Read a...

Page 165: ...A 52 ...

Page 166: ...mation on its in ternal status and its communication with the host This appendix describes the purpose and function of each register and provides many bitmaps and descrip tions of individual bits The appendix also describes the sequence of steps used for IEEE 802 12 100VG AnyLAN training which is used in opening ThunderLAN to the network Topic Page B 1 100VG AnyLAN Training B 2 B 2 TNETE211 Regist...

Page 167: ...the interrupt is handled then ThunderLAN is open on the wire Otherwise it is not Training between the client and hub is accomplished by exchanging 24 con secutive frames training frames between the client and hub These 24 frames must be exchanged within a window consisting of 48 frames If training is not accomplished within this window it can continue after a suitable delay in another 48 frame win...

Page 168: ...man timer before halting the transmitter 10 s ii Assert the Tx STOP interrupt by asserting the MASK5 bit in the NetMask register iii Issue a Tx STOP command by setting the STOP bit in the HOST_CMD register with the appropriate channel set iv Exit the routine and the service interrupt when the transmitter stops b If not transmitting do not use STOP 6 At this point use the following steps to build t...

Page 169: ...48 frames If this fails training may or may not be possible within this window The client must ensure that there are enough frames left in the window for successful training If this is not possible the client must re quest a new training window and try again The process is shown below Figure B 2 Training Flowchart Yes No No Yes No Yes training Restart Training successful Training failed window tra...

Page 170: ...dow does not allow the exchange of 24 frames the driver must request a new training window This can be accomplished by Setting the TRFAIL bit and clearing the TRIDLE bit in the TLPHY_ctl register Waiting for a status interrupt A deadman timer 10 s may be necessary to ensure that the driver does not sit indefinitely in this state Checking the RETRAIN bit in TLPHY_sts when status interrupt arrives R...

Page 171: ...2 12 media access controller MAC state machines The 100VG AnyLAN demand priority PHY registers are indirectly accessible through the MII management interface present in ThunderLAN This is a low speed serial interface which is supported on ThunderLAN through the NetSio register in adapter DIO space A host software program uses the MCLK MTXEN and MDATA bits in this register to implement the MII seri...

Page 172: ...EST ISOLATE PDOWN 0 LOOPBK RESET 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 Table B 1 PHY Generic Control Register Bits Bit Name Function 15 RESET PHY reset Writing a 1 to this bit causes the PHY and its internal registers to reset This bit is self clearing the bit returns a value of 1 when read until the internal reset is com plete This bit also serves to reset the 802 12 MAC state machine to MA...

Page 173: ...ver still respond to management frames on MDIO and MDCLK 9 0 Autoconfiguration enable Not implemented 8 0 Duplex mode VG currently does not support a full duplex mode 7 COLTEST Collision test mode Setting this bit to 1 causes the PHY to assert the collision sense signal MCOL whenever transmit enable MTXEN is asserted 6 0 Reserved Read as 0 Oscillator enable from the TNETE211 B 2 2 PHY Generic Stat...

Page 174: ...t indicates a jabber condition has been detected This bit is autoclearing and a jabber condition is latched held until the register is read 0 1 Extended capability This bit is hardwired to 1 to indicate that the extended register set is supported B 2 3 PHY Generic Identifier GEN_id_hi GEN_id_lo 0x2 0x3 These two hardwired 16 bit registers contain an identifier code for the ThunderLAN 100VG AnyLAN ...

Page 175: ...t Writing a 1 to this bit causes the PMI to indicate training idle to the PMD whenever there is no transmit request pending Writing a 0 to this bit causes the PMI to send idle up whenever there is no transmit request pending 3 NPMDW Not physical media dependant wrap This bit only has meaning when the LOOPBK bit of the GEN_ctl is a 1 Writing a 1 to this bit causes the PMI to wrap the Tx data to the...

Page 176: ...t can be determined by examining these bits In the case of LINK which could change before the interrupt type can be determined ThunderLAN keeps this bit as 0 until it is read even if the link is restored This is to ensure that the condition change is not lost 14 PHOK Power high OK This bit is reserved for future use 13 12 Reserved Read as 0s 11 8 CONFIG Configuration bits These bits indicate the t...

Page 177: ...raining idles from the repeater indicating that the station should enter training This bit is autoclearing and is latched until read If the INTEN bit is also set this causes an MII interrupt 1 LRCV Long receive This bit indicates that the PMI has detected a long receive receive jab ber condition from the PMA This bit is autoclearing and is latched until read If the INTEN bit is also set this cause...

Page 178: ...1 Appendix A TNETE100PM TNETE110PM For information on the TNETE100PM and TNETE110PM implementations of ThunderLAN please contact TLANHOT micro ti com which is listed on page v of this document Appendix C ...

Page 179: ...C 2 ...

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